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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IO 1 /* on a Io board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME io
Dirk Eibach28437152013-06-26 16:04:31 +020020#define CONFIG_IDENT_STRING " io 0.06"
Dirk Eibacha605ea72010-10-21 10:50:05 +020021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibachb19bf832012-04-26 03:54:23 +000025#define CONFIG_MISC_INIT_R
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000026#define CONFIG_LAST_STAGE_INIT
Dirk Eibacha605ea72010-10-21 10:50:05 +020027
28#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
29
30/*
31 * Configure PLL
32 */
33#define PLLMR0_DEFAULT PLLMR0_266_133_66
34#define PLLMR1_DEFAULT PLLMR1_266_133_66
35
Dirk Eibach996d88d2012-04-26 03:54:25 +000036#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach996d88d2012-04-26 03:54:25 +000037
Dirk Eibacha605ea72010-10-21 10:50:05 +020038/* new uImage format support */
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020041#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020042
43#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
44
45/*
46 * Default environment variables
47 */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4 /* PHY address */
58#define CONFIG_HAS_ETH0
59#define CONFIG_HAS_ETH1
60#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
62
63/*
64 * Commands additional to the ones defined in amcc-common.h
65 */
Dirk Eibachb19bf832012-04-26 03:54:23 +000066#define CONFIG_CMD_DTT
Dirk Eibach4fb9b412014-07-03 09:28:25 +020067#undef CONFIG_CMD_DHCP
68#undef CONFIG_CMD_DIAG
Dirk Eibacha605ea72010-10-21 10:50:05 +020069#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020070#undef CONFIG_CMD_I2C
71#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020072
73/*
74 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
75 */
76#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
77
78/* SDRAM timings used in datasheet */
79#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
80#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
81#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
82#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
83#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
84
85/*
86 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
87 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
88 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
89 * The Linux BASE_BAUD define should match this configuration.
90 * baseBaud = cpuClock/(uartDivisor*16)
91 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
92 * set Linux BASE_BAUD to 403200.
93 */
94#define CONFIG_CONS_INDEX 1 /* Use UART0 */
95#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
96#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
97#define CONFIG_SYS_BASE_BAUD 691200
98
99/*
100 * I2C stuff
101 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000102#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200103
104/* Temp sensor/hwmon/dtt */
105#define CONFIG_DTT_LM63 1 /* National LM63 */
106#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
107#define CONFIG_DTT_PWM_LOOKUPTABLE \
108 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
109#define CONFIG_DTT_TACH_LIMIT 0xa10
110
111/*
112 * FLASH organization
113 */
114#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
115#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
116
117#define CONFIG_SYS_FLASH_BASE 0xFC000000
118#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
119
120#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
121#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
122
123#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
125
126#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200127
128#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
129#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
130
131#ifdef CONFIG_ENV_IS_IN_FLASH
132#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
133#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
134#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
135
136/* Address and size of Redundant Environment Sector */
137#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
138#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
139#endif
140
141/* Gbit PHYs */
142#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
143#define CONFIG_BITBANGMII_MULTI
144
145#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
146#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
147
148#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
149
150/*
151 * PPC405 GPIO Configuration
152 */
153#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
154{ \
155/* GPIO Core 0 */ \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
157{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
158{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
159{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
160{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
162{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
164{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
165{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
166{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
167{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
169{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
170{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
171{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
172{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
174{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
176{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
177{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
178{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
179{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
180{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
181{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
182{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
183{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
184{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
185{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
186{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
187{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
188} \
189}
190
191/*
192 * Definitions for initial stack pointer and data area (in data cache)
193 */
194/* use on chip memory (OCM) for temperary stack until sdram is tested */
195#define CONFIG_SYS_TEMP_STACK_OCM 1
196
197/* On Chip Memory location */
198#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
199#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
200#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
201#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
202
Dirk Eibacha605ea72010-10-21 10:50:05 +0200203#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900204 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206
207/*
208 * External Bus Controller (EBC) Setup
209 */
210
211/* Memory Bank 0 (NOR-FLASH) initialization */
212#define CONFIG_SYS_EBC_PB0AP 0xa382a880
213/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
214#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
215
216/* Memory Bank 1 (NVRAM) initializatio */
217#define CONFIG_SYS_EBC_PB1AP 0x92015480
218/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
219#define CONFIG_SYS_EBC_PB1CR 0x7f318000
220
221/* Memory Bank 2 (FPGA) initialization */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100222#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200223#define CONFIG_SYS_EBC_PB2AP 0x02025080
224/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
225#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
226
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100227#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
228#define CONFIG_SYS_FPGA_DONE(k) 0x0010
229
230#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200231
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200232#define CONFIG_SYS_FPGA_PTR \
233 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
234
235#define CONFIG_SYS_FPGA_COMMON
236
Dirk Eibacha605ea72010-10-21 10:50:05 +0200237/* Memory Bank 3 (Latches) initialization */
238#define CONFIG_SYS_LATCH_BASE 0x7f200000
239#define CONFIG_SYS_EBC_PB3AP 0xa2015480
240/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
241#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
242
243#define CONFIG_SYS_LATCH0_RESET 0xffff
244#define CONFIG_SYS_LATCH0_BOOT 0xffff
245#define CONFIG_SYS_LATCH1_RESET 0xffbf
246#define CONFIG_SYS_LATCH1_BOOT 0xffff
247
248#endif /* __CONFIG_H */