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Sascha Hauer9b56f4f2008-03-26 20:40:42 +01001/*
2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19
20#include <common.h>
Ilya Yanok47d19da2009-06-08 04:12:46 +040021#ifdef CONFIG_MX31
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010022#include <asm/arch/mx31.h>
Ilya Yanok47d19da2009-06-08 04:12:46 +040023#else
24#include <asm/arch/imx-regs.h>
25#include <asm/arch/clock.h>
26#endif
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010027
28#define __REG(x) (*((volatile u32 *)(x)))
29
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#ifdef CONFIG_SYS_MX31_UART1
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010031#define UART_PHYS 0x43f90000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#elif defined(CONFIG_SYS_MX31_UART2)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010033#define UART_PHYS 0x43f94000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#elif defined(CONFIG_SYS_MX31_UART3)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010035#define UART_PHYS 0x5000c000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#elif defined(CONFIG_SYS_MX31_UART4)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010037#define UART_PHYS 0x43fb0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#elif defined(CONFIG_SYS_MX31_UART5)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010039#define UART_PHYS 0x43fb4000
Ilya Yanok47d19da2009-06-08 04:12:46 +040040#elif defined(CONFIG_SYS_MX27_UART1)
41#define UART_PHYS 0x1000a000
42#elif defined(CONFIG_SYS_MX27_UART2)
43#define UART_PHYS 0x1000b000
44#elif defined(CONFIG_SYS_MX27_UART3)
45#define UART_PHYS 0x1000c000
46#elif defined(CONFIG_SYS_MX27_UART4)
47#define UART_PHYS 0x1000d000
48#elif defined(CONFIG_SYS_MX27_UART5)
49#define UART_PHYS 0x1001b000
50#elif defined(CONFIG_SYS_MX27_UART6)
51#define UART_PHYS 0x1001c000
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010052#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010054#endif
55
56/* Register definitions */
57#define URXD 0x0 /* Receiver Register */
58#define UTXD 0x40 /* Transmitter Register */
59#define UCR1 0x80 /* Control Register 1 */
60#define UCR2 0x84 /* Control Register 2 */
61#define UCR3 0x88 /* Control Register 3 */
62#define UCR4 0x8c /* Control Register 4 */
63#define UFCR 0x90 /* FIFO Control Register */
64#define USR1 0x94 /* Status Register 1 */
65#define USR2 0x98 /* Status Register 2 */
66#define UESC 0x9c /* Escape Character Register */
67#define UTIM 0xa0 /* Escape Timer Register */
68#define UBIR 0xa4 /* BRM Incremental Register */
69#define UBMR 0xa8 /* BRM Modulator Register */
70#define UBRC 0xac /* Baud Rate Count Register */
71#define UTS 0xb4 /* UART Test Register (mx31) */
72
73/* UART Control Register Bit Fields.*/
74#define URXD_CHARRDY (1<<15)
75#define URXD_ERR (1<<14)
76#define URXD_OVRRUN (1<<13)
77#define URXD_FRMERR (1<<12)
78#define URXD_BRK (1<<11)
79#define URXD_PRERR (1<<10)
Juergen Kilbd92ea212008-06-08 17:59:53 +020080#define URXD_RX_DATA (0xFF)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010081#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020095#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010098#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100163#define UTS_SOFTRST (1<<0) /* Software reset */
164
165DECLARE_GLOBAL_DATA_PTR;
166
167void serial_setbrg (void)
168{
Ilya Yanok47d19da2009-06-08 04:12:46 +0400169#ifdef CONFIG_MX31
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100170 u32 clk = mx31_get_ipg_clk();
Ilya Yanok47d19da2009-06-08 04:12:46 +0400171#else
172 u32 clk = imx_get_perclk1();
173#endif
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100174
175 if (!gd->baudrate)
176 gd->baudrate = CONFIG_BAUDRATE;
177
178 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
179 __REG(UART_PHYS + UBIR) = 0xf;
180 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
181
182}
183
184int serial_getc (void)
185{
186 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
Juergen Kilbd92ea212008-06-08 17:59:53 +0200187 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100188}
189
190void serial_putc (const char c)
191{
192 __REG(UART_PHYS + UTXD) = c;
193
194 /* wait for transmitter to be ready */
195 while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
196
197 /* If \n, also do \r */
198 if (c == '\n')
199 serial_putc ('\r');
200}
201
202/*
203 * Test whether a character is in the RX buffer
204 */
205int serial_tstc (void)
206{
207 /* If receive fifo is empty, return false */
208 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
209 return 0;
210 return 1;
211}
212
213void
214serial_puts (const char *s)
215{
216 while (*s) {
217 serial_putc (*s++);
218 }
219}
220
221/*
222 * Initialise the serial port with the given baudrate. The settings
223 * are always 8 data bits, no parity, 1 stop bit, no start bits.
224 *
225 */
226int serial_init (void)
227{
228 __REG(UART_PHYS + UCR1) = 0x0;
229 __REG(UART_PHYS + UCR2) = 0x0;
230
231 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
232
233 __REG(UART_PHYS + UCR3) = 0x0704;
234 __REG(UART_PHYS + UCR4) = 0x8000;
235 __REG(UART_PHYS + UESC) = 0x002b;
236 __REG(UART_PHYS + UTIM) = 0x0;
237
238 __REG(UART_PHYS + UTS) = 0x0;
239
240 serial_setbrg();
241
242 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
243
244 __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
245
246 return 0;
247}