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Boris Brezillond13f5b22018-08-16 17:30:11 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Exceet Electronics GmbH
4 * Copyright (C) 2018 Bootlin
5 *
6 * Author:
7 * Peter Pan <peterpandong@micron.com>
8 * Boris Brezillon <boris.brezillon@bootlin.com>
9 */
10
11#ifndef __UBOOT_SPI_MEM_H
12#define __UBOOT_SPI_MEM_H
13
Simon Glass340fd102020-07-19 10:15:34 -060014struct udevice;
Boris Brezillond13f5b22018-08-16 17:30:11 +020015
16#define SPI_MEM_OP_CMD(__opcode, __buswidth) \
17 { \
18 .buswidth = __buswidth, \
19 .opcode = __opcode, \
Pratyush Yadavd15de622021-06-26 00:47:04 +053020 .nbytes = 1, \
Boris Brezillond13f5b22018-08-16 17:30:11 +020021 }
22
23#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
24 { \
25 .nbytes = __nbytes, \
26 .val = __val, \
27 .buswidth = __buswidth, \
28 }
29
30#define SPI_MEM_OP_NO_ADDR { }
31
32#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
33 { \
34 .nbytes = __nbytes, \
35 .buswidth = __buswidth, \
36 }
37
38#define SPI_MEM_OP_NO_DUMMY { }
39
40#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
41 { \
42 .dir = SPI_MEM_DATA_IN, \
43 .nbytes = __nbytes, \
44 .buf.in = __buf, \
45 .buswidth = __buswidth, \
46 }
47
48#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
49 { \
50 .dir = SPI_MEM_DATA_OUT, \
51 .nbytes = __nbytes, \
52 .buf.out = __buf, \
53 .buswidth = __buswidth, \
54 }
55
56#define SPI_MEM_OP_NO_DATA { }
57
58/**
59 * enum spi_mem_data_dir - describes the direction of a SPI memory data
60 * transfer from the controller perspective
Tudor Ambarus790c1692020-03-20 09:35:31 +000061 * @SPI_MEM_NO_DATA: no data transferred
Boris Brezillond13f5b22018-08-16 17:30:11 +020062 * @SPI_MEM_DATA_IN: data coming from the SPI memory
63 * @SPI_MEM_DATA_OUT: data sent the SPI memory
64 */
65enum spi_mem_data_dir {
Tudor Ambarus790c1692020-03-20 09:35:31 +000066 SPI_MEM_NO_DATA,
Boris Brezillond13f5b22018-08-16 17:30:11 +020067 SPI_MEM_DATA_IN,
68 SPI_MEM_DATA_OUT,
69};
70
71/**
72 * struct spi_mem_op - describes a SPI memory operation
Pratyush Yadavd15de622021-06-26 00:47:04 +053073 * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
74 * sent MSB-first.
Boris Brezillond13f5b22018-08-16 17:30:11 +020075 * @cmd.buswidth: number of IO lines used to transmit the command
76 * @cmd.opcode: operation opcode
Pratyush Yadava1eb40b2021-06-26 00:47:03 +053077 * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
Boris Brezillond13f5b22018-08-16 17:30:11 +020078 * @addr.nbytes: number of address bytes to send. Can be zero if the operation
79 * does not need to send an address
80 * @addr.buswidth: number of IO lines used to transmit the address cycles
81 * @addr.val: address value. This value is always sent MSB first on the bus.
82 * Note that only @addr.nbytes are taken into account in this
83 * address value, so users should make sure the value fits in the
84 * assigned number of bytes.
Pratyush Yadava1eb40b2021-06-26 00:47:03 +053085 * @addr.dtr: whether the address should be sent in DTR mode or not
Boris Brezillond13f5b22018-08-16 17:30:11 +020086 * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
87 * be zero if the operation does not require dummy bytes
88 * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
Pratyush Yadava1eb40b2021-06-26 00:47:03 +053089 * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
Boris Brezillond13f5b22018-08-16 17:30:11 +020090 * @data.buswidth: number of IO lanes used to send/receive the data
Pratyush Yadava1eb40b2021-06-26 00:47:03 +053091 * @data.dtr: whether the data should be sent in DTR mode or not
Boris Brezillond13f5b22018-08-16 17:30:11 +020092 * @data.dir: direction of the transfer
93 * @data.buf.in: input buffer
94 * @data.buf.out: output buffer
95 */
96struct spi_mem_op {
97 struct {
Pratyush Yadavd15de622021-06-26 00:47:04 +053098 u8 nbytes;
Boris Brezillond13f5b22018-08-16 17:30:11 +020099 u8 buswidth;
Pratyush Yadava1eb40b2021-06-26 00:47:03 +0530100 u8 dtr : 1;
Pratyush Yadavd15de622021-06-26 00:47:04 +0530101 u16 opcode;
Boris Brezillond13f5b22018-08-16 17:30:11 +0200102 } cmd;
103
104 struct {
105 u8 nbytes;
106 u8 buswidth;
Pratyush Yadava1eb40b2021-06-26 00:47:03 +0530107 u8 dtr : 1;
Boris Brezillond13f5b22018-08-16 17:30:11 +0200108 u64 val;
109 } addr;
110
111 struct {
112 u8 nbytes;
113 u8 buswidth;
Pratyush Yadava1eb40b2021-06-26 00:47:03 +0530114 u8 dtr : 1;
Boris Brezillond13f5b22018-08-16 17:30:11 +0200115 } dummy;
116
117 struct {
118 u8 buswidth;
Pratyush Yadava1eb40b2021-06-26 00:47:03 +0530119 u8 dtr : 1;
Boris Brezillond13f5b22018-08-16 17:30:11 +0200120 enum spi_mem_data_dir dir;
121 unsigned int nbytes;
122 /* buf.{in,out} must be DMA-able. */
123 union {
124 void *in;
125 const void *out;
126 } buf;
127 } data;
128};
129
130#define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \
131 { \
132 .cmd = __cmd, \
133 .addr = __addr, \
134 .dummy = __dummy, \
135 .data = __data, \
136 }
137
138#ifndef __UBOOT__
139/**
140 * struct spi_mem - describes a SPI memory device
141 * @spi: the underlying SPI device
142 * @drvpriv: spi_mem_driver private data
143 *
144 * Extra information that describe the SPI memory device and may be needed by
145 * the controller to properly handle this device should be placed here.
146 *
147 * One example would be the device size since some controller expose their SPI
148 * mem devices through a io-mapped region.
149 */
150struct spi_mem {
151 struct udevice *dev;
152 void *drvpriv;
153};
154
155/**
156 * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem
157 * device
158 * @mem: memory device
159 * @data: data to attach to the memory device
160 */
161static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data)
162{
163 mem->drvpriv = data;
164}
165
166/**
167 * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem
168 * device
169 * @mem: memory device
170 *
171 * Return: the data attached to the mem device.
172 */
173static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
174{
175 return mem->drvpriv;
176}
177#endif /* __UBOOT__ */
178
179/**
180 * struct spi_controller_mem_ops - SPI memory operations
181 * @adjust_op_size: shrink the data xfer of an operation to match controller's
182 * limitations (can be alignment of max RX/TX size
183 * limitations)
184 * @supports_op: check if an operation is supported by the controller
185 * @exec_op: execute a SPI memory operation
186 *
187 * This interface should be implemented by SPI controllers providing an
188 * high-level interface to execute SPI memory operation, which is usually the
189 * case for QSPI controllers.
190 */
191struct spi_controller_mem_ops {
192 int (*adjust_op_size)(struct spi_slave *slave, struct spi_mem_op *op);
193 bool (*supports_op)(struct spi_slave *slave,
194 const struct spi_mem_op *op);
195 int (*exec_op)(struct spi_slave *slave,
196 const struct spi_mem_op *op);
197};
198
199#ifndef __UBOOT__
200/**
201 * struct spi_mem_driver - SPI memory driver
202 * @spidrv: inherit from a SPI driver
203 * @probe: probe a SPI memory. Usually where detection/initialization takes
204 * place
205 * @remove: remove a SPI memory
206 * @shutdown: take appropriate action when the system is shutdown
207 *
208 * This is just a thin wrapper around a spi_driver. The core takes care of
209 * allocating the spi_mem object and forwarding the probe/remove/shutdown
210 * request to the spi_mem_driver. The reason we use this wrapper is because
211 * we might have to stuff more information into the spi_mem struct to let
212 * SPI controllers know more about the SPI memory they interact with, and
213 * having this intermediate layer allows us to do that without adding more
214 * useless fields to the spi_device object.
215 */
216struct spi_mem_driver {
217 struct spi_driver spidrv;
218 int (*probe)(struct spi_mem *mem);
219 int (*remove)(struct spi_mem *mem);
220 void (*shutdown)(struct spi_mem *mem);
221};
222
223#if IS_ENABLED(CONFIG_SPI_MEM)
224int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
225 const struct spi_mem_op *op,
226 struct sg_table *sg);
227
228void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
229 const struct spi_mem_op *op,
230 struct sg_table *sg);
231#else
232static inline int
233spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
234 const struct spi_mem_op *op,
235 struct sg_table *sg)
236{
Simon Glass24e3d5d2021-03-25 10:26:06 +1300237 return -ENOSYS;
Boris Brezillond13f5b22018-08-16 17:30:11 +0200238}
239
240static inline void
241spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
242 const struct spi_mem_op *op,
243 struct sg_table *sg)
244{
245}
246#endif /* CONFIG_SPI_MEM */
247#endif /* __UBOOT__ */
248
249int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
250
251bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
Pratyush Yadav5752d6a2021-06-26 00:47:06 +0530252bool spi_mem_dtr_supports_op(struct spi_slave *slave,
253 const struct spi_mem_op *op);
Boris Brezillond13f5b22018-08-16 17:30:11 +0200254
Pratyush Yadav22990762021-06-26 00:47:05 +0530255bool spi_mem_default_supports_op(struct spi_slave *slave,
256 const struct spi_mem_op *op);
257
Boris Brezillond13f5b22018-08-16 17:30:11 +0200258int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
259
Mathew McBrideaf6266c2021-01-25 03:55:20 +0000260bool spi_mem_default_supports_op(struct spi_slave *mem,
261 const struct spi_mem_op *op);
262
Boris Brezillond13f5b22018-08-16 17:30:11 +0200263#ifndef __UBOOT__
264int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
265 struct module *owner);
266
267void spi_mem_driver_unregister(struct spi_mem_driver *drv);
268
269#define spi_mem_driver_register(__drv) \
270 spi_mem_driver_register_with_owner(__drv, THIS_MODULE)
271
272#define module_spi_mem_driver(__drv) \
273 module_driver(__drv, spi_mem_driver_register, \
274 spi_mem_driver_unregister)
275#endif
276
277#endif /* __LINUX_SPI_MEM_H */