blob: 89ced824eb6721c7425195c0152be06fe7074f60 [file] [log] [blame]
Stefan Roese13b4f632012-08-14 15:04:19 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2006
9 * MicroSys GmbH
10 *
11 * Copyright 2012 Stefan Roese <sr@denx.de>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 */
21
22#include <common.h>
23#include <command.h>
24#include <mpc5xxx.h>
25#include <pci.h>
26#include <miiphy.h>
27#include <asm/processor.h>
28#include <asm/io.h>
29
30#include "mt46v16m16-75.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#if !defined(CONFIG_SYS_RAMBOOT) && \
35 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
36static void sdram_start(int hi_addr)
37{
38 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
39 long control = SDRAM_CONTROL | hi_addr_bit;
40
41 /* unlock mode register */
42 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
43
44 /* precharge all banks */
45 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
46
47#ifdef SDRAM_DDR
48 /* set mode register: extended mode */
49 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
50
51 /* set mode register: reset DLL */
52 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
53#endif
54
55 /* precharge all banks */
56 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
57
58 /* auto refresh */
59 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
60
61 /* set mode register */
62 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
63
64 /* normal operation */
65 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
66}
67#endif
68
69/*
70 * ATTENTION: Although partially referenced initdram does NOT make real use
71 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
72 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
73 */
74phys_size_t initdram(int board_type)
75{
76 ulong dramsize = 0;
77 ulong dramsize2 = 0;
78 uint svr, pvr;
79#if !defined(CONFIG_SYS_RAMBOOT) && \
80 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
81 ulong test1, test2;
82
83 /* setup SDRAM chip selects */
84 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
85 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
86
87 /* setup config registers */
88 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
89 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
90
91#ifdef SDRAM_DDR
92 /* set tap delay */
93 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
94#endif
95
96 /* find RAM size using SDRAM CS0 only */
97 sdram_start(0);
98 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
99 sdram_start(1);
100 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
101 if (test1 > test2) {
102 sdram_start(0);
103 dramsize = test1;
104 } else {
105 dramsize = test2;
106 }
107
108 /* memory smaller than 1MB is impossible */
109 if (dramsize < (1 << 20))
110 dramsize = 0;
111
112 /* set SDRAM CS0 size according to the amount of RAM found */
113 if (dramsize > 0) {
114 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
115 0x13 + __builtin_ffs(dramsize >> 20) - 1);
116 } else {
117 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
118 }
119#else /* CONFIG_SYS_RAMBOOT */
120
121 /* retrieve size of memory connected to SDRAM CS0 */
122 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
123 if (dramsize >= 0x13)
124 dramsize = (1 << (dramsize - 0x13)) << 20;
125 else
126 dramsize = 0;
127
128 /* retrieve size of memory connected to SDRAM CS1 */
129 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
130 if (dramsize2 >= 0x13)
131 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
132 else
133 dramsize2 = 0;
134
135#endif /* CONFIG_SYS_RAMBOOT */
136
137 /*
138 * On MPC5200B we need to set the special configuration delay in the
139 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
140 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
141 *
142 * "The SDelay should be written to a value of 0x00000004. It is
143 * required to account for changes caused by normal wafer processing
144 * parameters."
145 */
146 svr = get_svr();
147 pvr = get_pvr();
148 if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
149 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
150
151 return dramsize + dramsize2;
152}
153
154static void get_revisions(int *failsavelevel, int *digiboardversion,
155 int *fpgaversion)
156{
157 struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
158 u8 val;
159
160 /*
161 * Figure out failsavelevel
162 * see ticket dsvk#59
163 */
164 *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
165
166 /* read digitalboard-version from TMR[2..4] */
167 val = 0;
168 val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
169 val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
170 val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
171 *digiboardversion = val;
172
173 if (*digiboardversion == 0) {
174 *failsavelevel = 1; /* digiboard-version ok */
175
176 /* read fpga-version from TMR[5..7] */
177 val = 0;
178 val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
179 val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
180 val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
181 *fpgaversion = val;
182
183 if (*fpgaversion == 1)
184 *failsavelevel = 2; /* fpga-version ok */
185 }
186}
187
188/*
189 * This function is called from the SPL U-Boot version for
190 * early init stuff, that needs to be done for OS (e.g. Linux)
191 * booting. Doing it later in the real U-Boot would not work
192 * in case that the SPL U-Boot boots Linux directly.
193 */
194void spl_board_init(void)
195{
196 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
197 struct mpc5xxx_mmap_ctl *mm =
198 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
199 int digiboardversion;
200 int failsavelevel;
201 int fpgaversion;
202 u32 val;
203
204 get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
205
206 val = in_be32(&mm->ipbi_ws_ctrl);
207
208 /* first clear bits 19..21 (CS3...5) */
209 val &= ~((1 << 19) | (1 << 20) | (1 << 21));
210 if (failsavelevel == 2) {
211 /* FPGA ok */
212 val |= (1 << 19) | (1 << 21);
213 }
214
215 if (failsavelevel >= 1) {
216 /* at least digiboard-version ok */
217 val |= (1 << 20);
218 }
219
220 /* And write new value back to register */
221 out_be32(&mm->ipbi_ws_ctrl, val);
222
223 /*
224 * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
225 * as all 3 config versions (failsave level) have the same setup.
226 */
227
228 /*
229 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
230 * ticket #60
231 *
232 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
233 * set bit 0(msb) to 1
234 */
235 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
236
237 /* setup GPIOs for status-leds if needed - see ticket #57 */
238 if (failsavelevel > 0) {
239 /* digiboard-version is OK */
240 /* LED is LOW ACTIVE - so deactivate by set output to 1 */
241 gpio->simple_dvo |= 1 << (31 - 12);
242 gpio->simple_dvo |= 1 << (31 - 13);
243 /* set GPIO direction to output */
244 gpio->simple_ddr |= 1 << (31 - 12);
245 gpio->simple_ddr |= 1 << (31 - 13);
246 /* open drain config is set to "normal output" at reset */
247 /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
248 /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
249 /* enable as GPIO */
250 gpio->simple_gpioe |= 1 << (31 - 12);
251 gpio->simple_gpioe |= 1 << (31 - 13);
252 }
253
254 /* setup fpga irq - see ticket #65 */
255 if (failsavelevel > 1) {
256 /*
257 * The main irq initialisation is done in interrupts.c
258 * mpc5xxx_init_irq
259 */
260 struct mpc5xxx_intr *intr =
261 (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
262
263 setbits_be32(&intr->ctrl, 0x08C01801);
264
265 /*
266 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
267 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
268 */
269 }
270
271}
272
273int checkboard(void)
274{
275 int digiboardversion;
276 int failsavelevel;
277 int fpgaversion;
278
279 get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
280
281 puts("Board: A3M071\n");
282 printf("Rev: failsave level %u\n", failsavelevel);
283 printf(" digiboard IO version %u\n", digiboardversion);
284 if (failsavelevel > 0) /* only if fpga-version red */
285 printf(" fpga IO version %u\n", fpgaversion);
286
287 return 0;
288}
289
290/* miscellaneous platform dependent initialisations */
291int misc_init_r(void)
292{
293 /* adjust flash start and offset to detected values */
294 gd->bd->bi_flashstart = flash_info[0].start[0];
295 gd->bd->bi_flashoffset = 0;
296
297 /* adjust mapping */
298 out_be32((void *)MPC5XXX_BOOTCS_START,
299 START_REG(gd->bd->bi_flashstart));
300 out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
301 out_be32((void *)MPC5XXX_BOOTCS_STOP,
302 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
303 out_be32((void *)MPC5XXX_CS0_STOP,
304 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
305
306 return 0;
307}
308
309#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
310void ft_board_setup(void *blob, bd_t * bd)
311{
312 ft_cpu_setup(blob, bd);
313}
314#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
315
316#ifdef CONFIG_SPL_OS_BOOT
317/*
318 * A3M071 specific implementation of spl_start_uboot()
319 *
320 * RETURN
321 * 0 if booting into OS is selected (default)
322 * 1 if booting into U-Boot is selected
323 */
324int spl_start_uboot(void)
325{
326 char s[8];
327
328 env_init();
329 getenv_f("boot_os", s, sizeof(s));
330 if ((s != NULL) && (strcmp(s, "yes") == 0))
331 return 0;
332
333 return 1;
334}
335#endif