blob: 363a77d8a4e2ca92a99170b5d118aa9976556bc8 [file] [log] [blame]
Wolfgang Denkf11033e2007-01-15 13:41:04 +01001/*
Heiko Schocherca43ba12007-01-11 15:44:44 +01002 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
4 *
5 * (C) Copyright 2003
6 * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
7 * Derived from walnut.c
8 *
9 * (C) Copyright 2000
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 *
30 * $Log:$
31 */
32
33#include <common.h>
34#include <asm/processor.h>
35#include <asm/io.h>
Wolfgang Denk6d3e0102007-01-16 18:30:50 +010036#include "sc3.h"
Heiko Schocherca43ba12007-01-11 15:44:44 +010037#include <pci.h>
38#include <i2c.h>
39#include <malloc.h>
40
41#undef writel
42#undef writeb
43#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
44#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
45
46/* write only register to configure things in our CPLD */
47#define CPLD_CONTROL_1 0x79000102
48#define CPLD_VERSION 0x79000103
49
50#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
51
52static struct pci_controller hose={0,};
53
54/************************************************************
55 * Standard definition
56 ************************************************************/
57
58/* CPC0_CR0 Function ISA bus
59 - GPIO0
60 - GPIO1 -> Output: NAND-Command Latch Enable
61 - GPIO2 -> Output: NAND Address Latch Enable
62 - GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
63 - GPIO4 -> Output: NAND-Chip Enable
64 - GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
65 - GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
66 - GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
67 - GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
68 - GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
69 - GPIO10/CS1# -> CS1# NAND ISA-CS#0
70 - GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
71 - GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
72 - GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
73 - GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
74 - GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
75 - GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
76 - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
77 - GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
78 - GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
79 - GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
80 - GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
81 - GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
82 - GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
83 - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
84*/
85/*
86| CPLD register: io-space at offset 0x102 (write only)
87| 0
88| 1
89| 2 0=CS#4 USB CS#, 1=ISA or GP bus
90| 3
91| 4
92| 5
93| 6 1=enable faster IDE access
94| 7
95*/
96#define USB_CHIP_ENABLE 0x04
97#define IDE_BOOSTING 0x40
98
99/* --------------- USB stuff ------------------------------------- */
100#ifdef CONFIG_ISP1161_PRESENT
101/**
102 * initUsbHost- Initialize the Philips isp1161 HC part if present
103 * @cpldConfig: Pointer to value in write only CPLD register
104 *
105 * Initialize the USB host controller if present and fills the
106 * scratch register to inform the driver about used resources
107 */
108
109static void initUsbHost (unsigned char *cpldConfig)
110{
111 int i;
112 unsigned long usbBase;
113 /*
114 * Read back where init.S has located the USB chip
115 */
116 mtdcr (0x012, 0x04);
117 usbBase = mfdcr (0x013);
118 if (!(usbBase & 0x18000)) /* enabled? */
119 return;
120 usbBase &= 0xFFF00000;
121
122 /*
123 * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
124 */
125 writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
126
127 /*
128 * first check: is the controller assembled?
129 */
130 hcWriteWord (usbBase, 0x5555, HcScratch);
131 if (hcReadWord (usbBase, HcScratch) == 0x5555) {
132 hcWriteWord (usbBase, 0xAAAA, HcScratch);
133 if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
134 if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
135 return; /* this is not our controller */
136 /*
137 * try a software reset. This needs up to 10 seconds (see datasheet)
138 */
139 hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
140 for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
141 udelay (10);
142 if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
143 break;
144 }
145
146 if (!i)
147 return; /* the controller doesn't responding. Broken? */
148 /*
149 * OK. USB controller is ready. Initialize it in such way the later driver
150 * can us it (without any knowing about specific implementation)
151 */
152 hcWriteDWord (usbBase, 0x00000000, HcControl);
153 /*
154 * disable all interrupt sources. Because we
155 * don't know where we come from (hard reset, cold start, soft reset...)
156 */
157 hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
158 /*
159 * our current setup hardware configuration
160 * - every port power supply can switched indepently
161 * - every port can signal overcurrent
162 * - every port is "outside" and the devices are removeable
163 */
164 hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
165 hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
166 /*
167 * don't forget to switch off power supply of each port
168 * The later running driver can reenable them to find and use
169 * the (maybe) connected devices.
170 *
171 */
172 hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
173 hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
174 hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
175 hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
176 hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
177 hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
178 /*
179 * controller is present and usable
180 */
181 *cpldConfig |= USB_CHIP_ENABLE;
182 }
183 }
184}
185#endif
186
187#if defined(CONFIG_START_IDE)
188int board_start_ide(void)
189{
190 if (IS_CAMERON) {
191 puts ("no IDE on cameron board.\n");
192 return 0;
193 }
194 return 1;
195}
196#endif
197
198static int sc3_cameron_init (void)
199{
200 /* Set up the Memory Controller for the CAMERON version */
201 mtebc (pb4ap, 0x01805940);
202 mtebc (pb4cr, 0x7401a000);
203 mtebc (pb5ap, 0x01805940);
204 mtebc (pb5cr, 0x7401a000);
205 mtebc (pb6ap, 0x0);
206 mtebc (pb6cr, 0x0);
207 mtebc (pb7ap, 0x0);
208 mtebc (pb7cr, 0x0);
209 return 0;
210}
211
212void sc3_read_eeprom (void)
213{
214 uchar i2c_buffer[18];
215
216 i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
217 i2c_buffer[9] = 0;
218 setenv ("serial#", (char *)i2c_buffer);
219
220 /* read mac-address from eeprom */
221 i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
222 i2c_buffer[17] = 0;
223 i2c_buffer[16] = i2c_buffer[14];
224 i2c_buffer[15] = i2c_buffer[13];
225 i2c_buffer[14] = ':';
226 i2c_buffer[13] = i2c_buffer[12];
227 i2c_buffer[12] = i2c_buffer[11];
228 i2c_buffer[11] = ':';
229 i2c_buffer[8] = ':';
230 i2c_buffer[5] = ':';
231 i2c_buffer[2] = ':';
232 setenv ("ethaddr", (char *)i2c_buffer);
233}
234
235int board_early_init_f (void)
236{
237 /* write only register to configure things in our CPLD */
238 unsigned char cpldConfig_1=0x00;
239
240/*-------------------------------------------------------------------------+
241| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
242|
243| Note: IRQ 0 UART 0, active high; level sensitive
244| IRQ 1 UART 1, active high; level sensitive
245| IRQ 2 IIC, active high; level sensitive
246| IRQ 3 Ext. master, rising edge, edge sensitive
247| IRQ 4 PCI, active high; level sensitive
248| IRQ 5 DMA Channel 0, active high; level sensitive
249| IRQ 6 DMA Channel 1, active high; level sensitive
250| IRQ 7 DMA Channel 2, active high; level sensitive
251| IRQ 8 DMA Channel 3, active high; level sensitive
252| IRQ 9 Ethernet Wakeup, active high; level sensitive
253| IRQ 10 MAL System Error (SERR), active high; level sensitive
254| IRQ 11 MAL Tx End of Buffer, active high; level sensitive
255| IRQ 12 MAL Rx End of Buffer, active high; level sensitive
256| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
257| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
258| IRQ 15 Ethernet, active high; level sensitive
259| IRQ 16 External PCI SERR, active high; level sensitive
260| IRQ 17 ECC Correctable Error, active high; level sensitive
261| IRQ 18 PCI Power Management, active high; level sensitive
262|
263| IRQ 19 (EXT IRQ7 405GPr only)
264| IRQ 20 (EXT IRQ8 405GPr only)
265| IRQ 21 (EXT IRQ9 405GPr only)
266| IRQ 22 (EXT IRQ10 405GPr only)
267| IRQ 23 (EXT IRQ11 405GPr only)
268| IRQ 24 (EXT IRQ12 405GPr only)
269|
270| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
271| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
272| IRQ 27 (EXT IRQ 2) USB controller
273| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
274| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
275| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
276| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
277|
278| Direct Memory Access Controller Signal Polarities
279| DRQ0 active high (like ISA)
280| ACK0 active low (like ISA)
281| EOT0 active high (like ISA)
282| DRQ1 active high (like ISA)
283| ACK1 active low (like ISA)
284| EOT1 active high (like ISA)
285| DRQ2 active high (like ISA)
286| ACK2 active low (like ISA)
287| EOT2 active high (like ISA)
288| DRQ3 active high (like ISA)
289| ACK3 active low (like ISA)
290| EOT3 active high (like ISA)
291|
292+-------------------------------------------------------------------------*/
293
294 writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
295
296 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
297 mtdcr (uicer, 0x00000000); /* disable all ints */
298 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
299
300 if (IS_CAMERON) {
301 sc3_cameron_init();
302 mtdcr (0x0B6, 0x18000000);
303 mtdcr (uicpr, 0xFFFFFFF0);
304 mtdcr (uictr, 0x10001030);
305 } else {
306 mtdcr (0x0B6, 0x0000000);
307 mtdcr (uicpr, 0xFFFFFFE0);
308 mtdcr (uictr, 0x10000020);
309 }
310 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
311 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
312
313 /* setup other implementation specific details */
314 mtdcr (ecr, 0x60606000);
315
316 mtdcr (cntrl1, 0x000042C0);
317
318 if (IS_CAMERON) {
319 mtdcr (cntrl0, 0x01380000);
320 /* Setup the GPIOs */
321 writel (0x08008000, 0xEF600700); /* Output states */
322 writel (0x00000000, 0xEF600718); /* Open Drain control */
323 writel (0x68098000, 0xEF600704); /* Output control */
324 } else {
325 mtdcr (cntrl0,0x00080000);
326 /* Setup the GPIOs */
327 writel (0x08000000, 0xEF600700); /* Output states */
328 writel (0x14000000, 0xEF600718); /* Open Drain control */
329 writel (0x7C000000, 0xEF600704); /* Output control */
330 }
331
332 /* Code decompression disabled */
333 mtdcr (kiar, kconf);
334 mtdcr (kidr, 0x2B);
335
336 /* CPC0_ER: enable sleep mode of (currently) unused components */
337 /* CPC0_FR: force unused components into sleep mode */
338 mtdcr (cpmer, 0x3F800000);
339 mtdcr (cpmfr, 0x14000000);
340
341 /* set PLB priority */
342 mtdcr (0x87, 0x08000000);
343
344 /* --------------- DMA stuff ------------------------------------- */
345 mtdcr (0x126, 0x49200000);
346
347#ifndef IDE_USES_ISA_EMULATION
348 cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
349 /* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
350 writeb (cpldConfig_1, CPLD_CONTROL_1);
351#endif
352
353#ifdef CONFIG_ISP1161_PRESENT
354 initUsbHost (&cpldConfig_1);
355 writeb (cpldConfig_1, CPLD_CONTROL_1);
356#endif
Heiko Schochercb482072007-01-18 11:28:51 +0100357 /* FIXME: for what must we do this */
358 *(unsigned long *)0x79000080 = 0x0001;
Heiko Schocherca43ba12007-01-11 15:44:44 +0100359 return(0);
360}
361
362int misc_init_r (void)
363{
364 char *s1;
365 int i, xilinx_val;
366 volatile char *xilinx_adr;
367 xilinx_adr = (char *)0x79000102;
368
369 *xilinx_adr = 0x00;
370
371/* customer settings ***************************************** */
372/*
373 s1 = getenv ("function");
374 if (s1) {
375 if (!strcmp (s1, "Rosho")) {
376 printf ("function 'Rosho' activated\n");
377 *xilinx_adr = 0x40;
378 }
379 else {
380 printf (">>>>>>>>>> function %s not recognized\n",s1);
381 }
382 }
383*/
384
385/* individual settings ***************************************** */
386 if ((s1 = getenv ("xilinx"))) {
387 i=0;
388 xilinx_val = 0;
389 while (i < 3 && s1[i]) {
390 if (s1[i] >= '0' && s1[i] <= '9')
391 xilinx_val = (xilinx_val << 4) + s1[i] - '0';
392 else
393 if (s1[i] >= 'A' && s1[i] <= 'F')
394 xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
395 else
396 if (s1[i] >= 'a' && s1[i] <= 'f')
397 xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
398 else {
399 xilinx_val = -1;
400 break;
401 }
402 i++;
403 }
404 if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
405 printf ("Xilinx: set to %s\n", s1);
406 *xilinx_adr = (unsigned char) xilinx_val;
407 } else
408 printf ("Xilinx: rejected value %s\n", s1);
409 }
410 return 0;
411}
412
413/* -------------------------------------------------------------------------
414 * printCSConfig
415 *
416 * Print some informations about chips select configurations
417 * Only used while debugging.
418 *
419 * Params:
420 * - No. of CS pin
421 * - AP of this CS
422 * - CR of this CS
423 *
424 * Returns
425 * nothing
426 ------------------------------------------------------------------------- */
427
428#ifdef SC3_DEBUGOUT
429static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
430{
431 const char *bsize[4] = {"8","16","32","?"};
432 const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
433 const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
434
435#define CYCLE 30 /* time of one clock (based on 33MHz) */
436
437 printf("\nCS#%d",reg);
438 if (!(cr & 0x00018000))
439 puts(" unused");
440 else {
441 if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
442 puts(" Address is not multiple of bank size!");
443
444 printf("\n -%s bit device",
445 bsize[(cr & 0x00006000) >> 13]);
446 printf(" at 0x%08lX", cr & 0xFFF00000U);
447 printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
448 printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
449 if (ap & 0x80000000) {
450 printf("\n -Burst device (%luns/%luns)",
451 (((ap & 0x7C000000) >> 26) + 1) * CYCLE,
452 (((ap & 0x03800000) >> 23) + 1) * CYCLE);
453 } else {
454 printf("\n -Non burst device, active cycle %luns",
455 (((ap & 0x7F800000) >> 23) + 1) * CYCLE);
456 printf("\n -Address setup %luns",
457 ((ap & 0xC0000) >> 18) * CYCLE);
458 printf("\n -CS active to RD %luns/WR %luns",
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100459 ((ap & 0x30000) >> 16) * CYCLE,
Heiko Schocherca43ba12007-01-11 15:44:44 +0100460 ((ap & 0xC000) >> 14) * CYCLE);
461 printf("\n -WR to CS inactive %luns",
462 ((ap & 0x3000) >> 12) * CYCLE);
463 printf("\n -Hold after access %luns",
464 ((ap & 0xE00) >> 9) * CYCLE);
465 printf("\n -Ready is %sabled",
466 ap & 0x100 ? "en" : "dis");
467 }
468 }
469}
470#endif
471
472#ifdef SC3_DEBUGOUT
473
474static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
475 pb5ap, pb6ap, pb7ap};
476static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
477 pb5cr, pb6cr, pb7cr};
478
479static int show_reg (int nr)
480{
481 unsigned long ul1, ul2;
482
483 mtdcr (ebccfga, ap[nr]);
484 ul1 = mfdcr (ebccfgd);
485 mtdcr (ebccfga, cr[nr]);
486 ul2 = mfdcr(ebccfgd);
487 printCSConfig(nr, ul1, ul2);
488 return 0;
489}
490#endif
491
492int checkboard (void)
493{
494#ifdef SC3_DEBUGOUT
495 unsigned long ul1;
496 int i;
497
498 for (i = 0; i < 8; i++) {
499 show_reg (i);
500 }
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100501
Heiko Schocherca43ba12007-01-11 15:44:44 +0100502 mtdcr (ebccfga, epcr);
503 ul1 = mfdcr (ebccfgd);
504
505 puts ("\nGeneral configuration:\n");
506
507 if (ul1 & 0x80000000)
508 printf(" -External Bus is always driven\n");
509
510 if (ul1 & 0x400000)
511 printf(" -CS signals are always driven\n");
512
513 if (ul1 & 0x20000)
514 printf(" -PowerDown after %lu clocks\n",
515 (ul1 & 0x1F000) >> 7);
516
517 switch (ul1 & 0xC0000)
518 {
519 case 0xC0000:
520 printf(" -No external master present\n");
521 break;
522 case 0x00000:
523 printf(" -8 bit external master present\n");
524 break;
525 case 0x40000:
526 printf(" -16 bit external master present\n");
527 break;
528 case 0x80000:
529 printf(" -32 bit external master present\n");
530 break;
531 }
532
533 switch (ul1 & 0x300000)
534 {
535 case 0x300000:
536 printf(" -Prefetch: Illegal setting!\n");
537 break;
538 case 0x000000:
539 printf(" -1 doubleword prefetch\n");
540 break;
541 case 0x100000:
542 printf(" -2 doublewords prefetch\n");
543 break;
544 case 0x200000:
545 printf(" -4 doublewords prefetch\n");
546 break;
547 }
548 putc ('\n');
549#endif
550 printf("Board: SolidCard III %s %s version.\n",
551 (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
552 return 0;
553}
554
555static int printSDRAMConfig(char reg, unsigned long cr)
556{
557 const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
558#ifdef SC3_DEBUGOUT
559 const char *basize[8]=
560 {"4", "8", "16", "32", "64", "128", "256", "Reserved"};
561
562 printf("SDRAM bank %d",reg);
563
564 if (!(cr & 0x01))
565 puts(" disabled\n");
566 else {
567 printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
568 printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
569 }
570#endif
571
572 if (cr & 0x01)
573 return(bisize[(cr & 0xE0000) >> 17]);
574
575 return 0;
576}
577
578#ifdef SC3_DEBUGOUT
579static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
580#endif
581
582long int initdram (int board_type)
583{
584 unsigned int mems=0;
585 unsigned long ul1;
586
587#ifdef SC3_DEBUGOUT
588 unsigned long ul2;
589 int i;
590
591 puts("\nSDRAM configuration:\n");
592
593 mtdcr (memcfga, mem_mcopt1);
594 ul1 = mfdcr(memcfgd);
595
596 if (!(ul1 & 0x80000000)) {
597 puts(" Controller disabled\n");
598 return 0;
599 }
600 for (i = 0; i < 4; i++) {
601 mtdcr (memcfga, mbcf[i]);
602 ul1 = mfdcr (memcfgd);
603 mems += printSDRAMConfig (i, ul1);
604 }
605
606 mtdcr (memcfga, mem_sdtr1);
607 ul1 = mfdcr(memcfgd);
608
609 printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
610 printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
611 printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
612 printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
613 printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
614 printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
615 puts ("Misc:\n");
616 mtdcr (memcfga, mem_rtr);
617 ul1 = mfdcr(memcfgd);
618 printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
619
620 mtdcr(memcfga,mem_pmit);
621 ul2=mfdcr(memcfgd);
622
623 mtdcr(memcfga,mem_mcopt1);
624 ul1=mfdcr(memcfgd);
625
626 if (ul1 & 0x20000000)
627 printf(" -Power Down after: %luns\n",
628 ((ul2 & 0xFFC00000) >> 22) * 7);
629 else
630 puts(" -Power Down disabled\n");
631
632 if (ul1 & 0x40000000)
633 printf(" -Self refresh feature active\n");
634 else
635 puts(" -Self refresh disabled\n");
636
637 if (ul1 & 0x10000000)
638 puts(" -ECC enabled\n");
639 else
640 puts(" -ECC disabled\n");
641
642 if (ul1 & 0x8000000)
643 puts(" -Using registered SDRAM\n");
644
645 if (!(ul1 & 0x6000000))
646 puts(" -Using 32 bit data width\n");
647 else
648 puts(" -Illegal data width!\n");
649
650 if (ul1 & 0x400000)
651 puts(" -ECC drivers inactive\n");
652 else
653 puts(" -ECC drivers active\n");
654
655 if (ul1 & 0x200000)
656 puts(" -Memory lines always active outputs\n");
657 else
658 puts(" -Memory lines only at write cycles active outputs\n");
659
660 mtdcr (memcfga, mem_status);
661 ul1 = mfdcr (memcfgd);
662 if (ul1 & 0x80000000)
663 puts(" -SDRAM Controller ready\n");
664 else
665 puts(" -SDRAM Controller not ready\n");
666
667 if (ul1 & 0x4000000)
668 puts(" -SDRAM in self refresh mode!\n");
669
670 return (mems * 1024 * 1024);
671#else
672 mtdcr (memcfga, mem_mb0cf);
673 ul1 = mfdcr (memcfgd);
674 mems = printSDRAMConfig (0, ul1);
675
676 mtdcr (memcfga, mem_mb1cf);
677 ul1 = mfdcr (memcfgd);
678 mems += printSDRAMConfig (1, ul1);
679
680 mtdcr (memcfga, mem_mb2cf);
681 ul1 = mfdcr(memcfgd);
682 mems += printSDRAMConfig (2, ul1);
683
684 mtdcr (memcfga, mem_mb3cf);
685 ul1 = mfdcr(memcfgd);
686 mems += printSDRAMConfig (3, ul1);
687
688 return (mems * 1024 * 1024);
689#endif
690}
691
692static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
693{
694/*-------------------------------------------------------------------------+
695 | ,-. ,-. ,-. ,-. ,-.
696 | INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
697 | |R| |C| \ / |C| \ / |E| \ / |r|
698 | INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
699 | |D| |0| \/ |0| \/ |h| \/ |f|
700 | INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
701 | |E| |+| /\ |+| /\ |r| /\ |k|
702 | INTA# ----| |-----| |- `----| |- `----| |- `----| |
703 | `-' `-' `-' `-' `-'
704 | Slot 0 10 11 12 13
705 | REQ# 0 1 2 *
706 | GNT# 0 1 2 *
707 +-------------------------------------------------------------------------*/
708 unsigned char int_line = 0xff;
709
710 switch (PCI_DEV(dev)) {
711 case 10:
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100712 int_line = 31; /* INT A */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100713 POST_OUT(0x42);
714 break;
715
716 case 11:
717 int_line = 30; /* INT B */
718 POST_OUT(0x43);
719 break;
720
721 case 12:
722 int_line = 29; /* INT C */
723 POST_OUT(0x44);
724 break;
725
726 case 13:
727 int_line = 28; /* INT D */
728 POST_OUT(0x45);
729 break;
730 }
731 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
732}
733
734extern void pci_405gp_init(struct pci_controller *hose);
735extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
736extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
737/*
738 * The following table is used when there is a special need to setup a PCI device.
739 * For every PCI device found in this table is called the given init function with given
740 * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
741 * parameters!
742 *
743*/
744static struct pci_config_table pci_solidcard3_config_table[] =
745{
746/* Host to PCI Bridge device (405GP) */
747 {
748 vendor: 0x1014,
749 device: 0x0156,
750 class: PCI_CLASS_BRIDGE_HOST,
751 bus: 0,
752 dev: 0,
753 func: 0,
754 config_device: pci_405gp_setup_bridge
755 },
756 { }
757};
758
759/*-------------------------------------------------------------------------+
760 | pci_init_board (Called from pci_init() in drivers/pci.c)
761 |
762 | Init the PCI part of the SolidCard III
763 |
764 | Params:
765 * - Pointer to current PCI hose
766 * - Current Device
767 *
768 * Returns
769 * nothing
770 +-------------------------------------------------------------------------*/
771
772void pci_init_board(void)
773{
774 POST_OUT(0x41);
775/*
776 * we want the ptrs to RAM not flash (ie don't use init list)
777 */
778 hose.fixup_irq = pci_solidcard3_fixup_irq;
779 hose.config_table = pci_solidcard3_config_table;
780 pci_405gp_init(&hose);
781}