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wdenk138ff602004-12-16 15:52:40 +00001/*
Detlev Zundel7b5611c2009-03-30 00:31:34 +02002 * (C) Copyright 2008-2009
3 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
4 *
5 * (C) Copyright 2009
6 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
wdenk138ff602004-12-16 15:52:40 +00007 *
8 * (C) Copyright 2004
9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
10 *
11 * (C) Copyright 2004
12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
13 *
Detlev Zundel7b5611c2009-03-30 00:31:34 +020014 * (C) Copyright 2003-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
16 *
wdenk138ff602004-12-16 15:52:40 +000017 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
Detlev Zundele979e852009-03-30 00:31:35 +020036#include <asm/io.h>
wdenk138ff602004-12-16 15:52:40 +000037#include <common.h>
38#include <mpc5xxx.h>
39#include <pci.h>
40
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010041#if defined(CONFIG_DDR_MT46V16M16)
wdenk138ff602004-12-16 15:52:40 +000042#include "mt46v16m16-75.h"
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010043#elif defined(CONFIG_SDR_MT48LC16M16A2)
wdenk138ff602004-12-16 15:52:40 +000044#include "mt48lc16m16a2-75.h"
Marian Balakowicz5fb6d712007-11-15 13:29:55 +010045#elif defined(CONFIG_DDR_MT46V32M16)
46#include "mt46v32m16.h"
47#elif defined(CONFIG_DDR_HYB25D512160BF)
48#include "hyb25d512160bf.h"
49#elif defined(CONFIG_DDR_K4H511638C)
50#include "k4h511638c.h"
51#else
52#error "INKA4x0 SDRAM: invalid chip type specified!"
wdenk138ff602004-12-16 15:52:40 +000053#endif
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#ifndef CONFIG_SYS_RAMBOOT
wdenk138ff602004-12-16 15:52:40 +000056static void sdram_start (int hi_addr)
57{
Detlev Zundel2344bb82009-03-30 00:31:36 +020058 volatile struct mpc5xxx_sdram *sdram =
59 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
wdenk138ff602004-12-16 15:52:40 +000060 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
61
62 /* unlock mode register */
Detlev Zundel2344bb82009-03-30 00:31:36 +020063 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000064
65 /* precharge all banks */
Detlev Zundel2344bb82009-03-30 00:31:36 +020066 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000067
68#if SDRAM_DDR
69 /* set mode register: extended mode */
Detlev Zundel2344bb82009-03-30 00:31:36 +020070 out_be32(&sdram->mode, SDRAM_EMODE);
wdenk138ff602004-12-16 15:52:40 +000071
72 /* set mode register: reset DLL */
Detlev Zundel2344bb82009-03-30 00:31:36 +020073 out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
wdenk138ff602004-12-16 15:52:40 +000074#endif
75
76 /* precharge all banks */
Detlev Zundel2344bb82009-03-30 00:31:36 +020077 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000078
79 /* auto refresh */
Detlev Zundel2344bb82009-03-30 00:31:36 +020080 out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000081
82 /* set mode register */
Detlev Zundel2344bb82009-03-30 00:31:36 +020083 out_be32(&sdram->mode, SDRAM_MODE);
wdenk138ff602004-12-16 15:52:40 +000084
85 /* normal operation */
Detlev Zundel2344bb82009-03-30 00:31:36 +020086 out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
wdenk138ff602004-12-16 15:52:40 +000087}
88#endif
89
90/*
91 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
wdenk138ff602004-12-16 15:52:40 +000093 * is something else than 0x00000000.
94 */
95
Becky Bruce9973e3c2008-06-09 16:03:40 -050096phys_size_t initdram (int board_type)
wdenk138ff602004-12-16 15:52:40 +000097{
Detlev Zundel2344bb82009-03-30 00:31:36 +020098 volatile struct mpc5xxx_mmap_ctl *mm =
99 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
100 volatile struct mpc5xxx_cdm *cdm =
101 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
102 volatile struct mpc5xxx_sdram *sdram =
103 (struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
wdenk138ff602004-12-16 15:52:40 +0000104 ulong dramsize = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#ifndef CONFIG_SYS_RAMBOOT
Marian Balakowiczf23cb342007-11-15 13:24:43 +0100106 long test1, test2;
wdenk138ff602004-12-16 15:52:40 +0000107
108 /* setup SDRAM chip selects */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200109 out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
110 out_be32(&mm->sdram1, 0x40000000); /* disabled */
wdenk138ff602004-12-16 15:52:40 +0000111
112 /* setup config registers */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200113 out_be32(&sdram->config1, SDRAM_CONFIG1);
114 out_be32(&sdram->config2, SDRAM_CONFIG2);
wdenk138ff602004-12-16 15:52:40 +0000115
116#if SDRAM_DDR
117 /* set tap delay */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200118 out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
wdenk138ff602004-12-16 15:52:40 +0000119#endif
120
121 /* find RAM size using SDRAM CS0 only */
122 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk138ff602004-12-16 15:52:40 +0000124 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk138ff602004-12-16 15:52:40 +0000126 if (test1 > test2) {
127 sdram_start(0);
128 dramsize = test1;
129 } else {
130 dramsize = test2;
131 }
132
133 /* memory smaller than 1MB is impossible */
134 if (dramsize < (1 << 20)) {
135 dramsize = 0;
136 }
137
138 /* set SDRAM CS0 size according to the amount of RAM found */
139 if (dramsize > 0) {
Detlev Zundel2344bb82009-03-30 00:31:36 +0200140 out_be32(&mm->sdram0, 0x13 +
141 __builtin_ffs(dramsize >> 20) - 1);
wdenk138ff602004-12-16 15:52:40 +0000142 } else {
Detlev Zundel2344bb82009-03-30 00:31:36 +0200143 out_be32(&mm->sdram0, 0); /* disabled */
wdenk138ff602004-12-16 15:52:40 +0000144 }
145
Detlev Zundel2344bb82009-03-30 00:31:36 +0200146 out_be32(&mm->sdram1, dramsize); /* disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#else /* CONFIG_SYS_RAMBOOT */
wdenk138ff602004-12-16 15:52:40 +0000148
149 /* retrieve size of memory connected to SDRAM CS0 */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200150 dramsize = in_be32(&mm->sdram0) & 0xFF;
wdenk138ff602004-12-16 15:52:40 +0000151 if (dramsize >= 0x13) {
152 dramsize = (1 << (dramsize - 0x13)) << 20;
153 } else {
154 dramsize = 0;
155 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#endif /* CONFIG_SYS_RAMBOOT */
wdenk138ff602004-12-16 15:52:40 +0000157
wdenk138ff602004-12-16 15:52:40 +0000158 return dramsize;
159}
160
161int checkboard (void)
162{
wdenk08f27272004-12-19 21:39:27 +0000163 puts ("Board: INKA 4X0\n");
wdenk138ff602004-12-16 15:52:40 +0000164 return 0;
165}
166
167void flash_preinit(void)
168{
Detlev Zundel2344bb82009-03-30 00:31:36 +0200169 volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
170
wdenk138ff602004-12-16 15:52:40 +0000171 /*
172 * Now, when we are in RAM, enable flash write
173 * access for detection process.
Detlev Zundel2344bb82009-03-30 00:31:36 +0200174 * Note that CS_BOOT (CS0) cannot be cleared when
wdenk138ff602004-12-16 15:52:40 +0000175 * executing in flash.
176 */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200177 clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
wdenk138ff602004-12-16 15:52:40 +0000178}
wdenk436be292005-01-31 22:09:11 +0000179
Detlev Zundel7b5611c2009-03-30 00:31:34 +0200180int misc_init_r (void) {
181 extern int inkadiag_init_r (void);
182
183 /*
184 * The command table used for the subcommands of inkadiag
185 * needs to be relocated manually.
186 */
187 return inkadiag_init_r();
188}
189
wdenk151ab832005-02-24 22:44:16 +0000190int misc_init_f (void)
191{
Detlev Zundel2344bb82009-03-30 00:31:36 +0200192 volatile struct mpc5xxx_gpio *gpio =
193 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
194 volatile struct mpc5xxx_wu_gpio *wu_gpio =
195 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
196 volatile struct mpc5xxx_gpt *gpt;
Marian Balakowiczf23cb342007-11-15 13:24:43 +0100197 char tmp[10];
wdenka0bdf492005-03-14 13:14:58 +0000198 int i, br;
199
200 i = getenv_r("brightness", tmp, sizeof(tmp));
201 br = (i > 0)
202 ? (int) simple_strtoul (tmp, NULL, 10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 : CONFIG_SYS_BRIGHTNESS;
wdenka0bdf492005-03-14 13:14:58 +0000204 if (br > 255)
205 br = 255;
206
wdenkf4733a02005-03-06 01:21:30 +0000207 /* Initialize GPIO output pins.
208 */
wdenk342717f2005-06-27 13:30:03 +0000209 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200210 for (i = 0; i <= 5; i++) {
211 gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
212 out_be32(&gpt->emsr, 0x34);
213 }
wdenkf4733a02005-03-06 01:21:30 +0000214
wdenka0bdf492005-03-14 13:14:58 +0000215 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200216 gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
217 out_be32(&gpt->emsr, 0); /* Disable */
218 out_be32(&gpt->cir, 0x020000fe);
219 out_be32(&gpt->pwmcr, (br << 16));
220 out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
wdenkf4733a02005-03-06 01:21:30 +0000221
222 /* Configure PSC3_6,7 as GPIO output */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200223 setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
224 MPC5XXX_GPIO_SIMPLE_PSC3_7);
225 setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
226 MPC5XXX_GPIO_SIMPLE_PSC3_7);
wdenkf4733a02005-03-06 01:21:30 +0000227
228 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200229 setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 |
230 MPC5XXX_GPIO_WKUP_7 |
231 MPC5XXX_GPIO_WKUP_PSC3_9);
232 setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 |
233 MPC5XXX_GPIO_WKUP_7 |
234 MPC5XXX_GPIO_WKUP_PSC3_9);
wdenkf4733a02005-03-06 01:21:30 +0000235
wdenk342717f2005-06-27 13:30:03 +0000236 /* Set LR mirror bit because it is low-active */
Detlev Zundel2344bb82009-03-30 00:31:36 +0200237 setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
238
239 /* Reset Coral-P graphics controller */
240 setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
241
242 /* Enable display backlight */
243 clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
244 setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
245 setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
246 setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
Detlev Zundele979e852009-03-30 00:31:35 +0200247
248 /*
249 * Configure three wire serial interface to RTC (PSC1_4,
250 * PSC2_4, PSC3_4, PSC3_5)
251 */
252 setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
253 MPC5XXX_GPIO_WKUP_PSC2_4);
254 setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
255 MPC5XXX_GPIO_WKUP_PSC2_4);
256 clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
257 clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
258 MPC5XXX_GPIO_SINT_PSC3_5);
259 setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
260 MPC5XXX_GPIO_SINT_PSC3_5);
261 setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
262 clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
263
wdenkf4733a02005-03-06 01:21:30 +0000264 return 0;
wdenk151ab832005-02-24 22:44:16 +0000265}
266
wdenkf4733a02005-03-06 01:21:30 +0000267#ifdef CONFIG_PCI
wdenk436be292005-01-31 22:09:11 +0000268static struct pci_controller hose;
269
270extern void pci_mpc5xxx_init(struct pci_controller *);
271
272void pci_init_board(void)
273{
wdenkf4733a02005-03-06 01:21:30 +0000274 pci_mpc5xxx_init(&hose);
wdenk436be292005-01-31 22:09:11 +0000275}
276#endif