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Julien May5c374c92008-06-23 13:57:52 +02001/*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Configuration settings for the Miromico Hammerhead AVR32 board
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Andreas Bießmannbf018332011-04-18 04:12:41 +000027#define CONFIG_AVR32
28#define CONFIG_AT32AP
29#define CONFIG_AT32AP7000
30#define CONFIG_HAMMERHEAD
Julien May5c374c92008-06-23 13:57:52 +020031
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_HZ 1000
Julien May5c374c92008-06-23 13:57:52 +020033
34/*
35 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
36 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
37 * and the PBA bus to run at 1/4 the PLL frequency.
38 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000039#define CONFIG_PLL
40#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_OSC0_HZ 25000000
42#define CONFIG_SYS_PLL0_DIV 1
43#define CONFIG_SYS_PLL0_MUL 5
44#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
45#define CONFIG_SYS_CLKDIV_CPU 0
46#define CONFIG_SYS_CLKDIV_HSB 1
47#define CONFIG_SYS_CLKDIV_PBA 2
48#define CONFIG_SYS_CLKDIV_PBB 1
Julien May5c374c92008-06-23 13:57:52 +020049
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070050/* Reserve VM regions for SDRAM and NOR flash */
51#define CONFIG_SYS_NR_VM_REGIONS 2
52
Julien May5c374c92008-06-23 13:57:52 +020053/*
54 * The PLLOPT register controls the PLL like this:
55 * icp = PLLOPT<2>
56 * ivco = PLLOPT<1:0>
57 *
58 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_PLL0_OPT 0x04
Julien May5c374c92008-06-23 13:57:52 +020061
Andreas Bießmannf4278b72010-11-04 23:15:31 +000062#define CONFIG_USART_BASE ATMEL_BASE_USART1
63#define CONFIG_USART_ID 1
Julien May5c374c92008-06-23 13:57:52 +020064
65#define CONFIG_HOSTNAME hammerhead
66
67/* User serviceable stuff */
Andreas Bießmannbf018332011-04-18 04:12:41 +000068#define CONFIG_DOS_PARTITION
Julien May5c374c92008-06-23 13:57:52 +020069
Andreas Bießmannbf018332011-04-18 04:12:41 +000070#define CONFIG_CMDLINE_TAG
71#define CONFIG_SETUP_MEMORY_TAGS
72#define CONFIG_INITRD_TAG
Julien May5c374c92008-06-23 13:57:52 +020073
74#define CONFIG_STACKSIZE (2048)
75
76#define CONFIG_BAUDRATE 115200
77#define CONFIG_BOOTARGS \
78 "console=ttyS0 root=mtd1 rootfstype=jffs2"
79#define CONFIG_BOOTCOMMAND \
80 "fsload; bootm"
81
82/*
83 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
84 * data on the serial line may interrupt the boot sequence.
85 */
86#define CONFIG_BOOTDELAY 1
Andreas Bießmannbf018332011-04-18 04:12:41 +000087#define CONFIG_AUTOBOOT
88#define CONFIG_AUTOBOOT_KEYED
Julien May5c374c92008-06-23 13:57:52 +020089#define CONFIG_AUTOBOOT_PROMPT \
Haavard Skinnemoen33eac2b2008-08-20 09:28:36 +020090 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Julien May5c374c92008-06-23 13:57:52 +020091#define CONFIG_AUTOBOOT_DELAY_STR "d"
92#define CONFIG_AUTOBOOT_STOP_STR " "
93
94/*
95 * After booting the board for the first time, new ethernet address
96 * should be generated and assigned to the environment variables
97 * "ethaddr". This is normally done during production.
98 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000099#define CONFIG_OVERWRITE_ETHADDR_ONCE
Julien May5c374c92008-06-23 13:57:52 +0200100
101/*
102 * BOOTP/DHCP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106
107/*
108 * Command line configuration.
109 */
110#include <config_cmd_default.h>
111
112#define CONFIG_CMD_ASKENV
113#define CONFIG_CMD_DHCP
114#define CONFIG_CMD_EXT2
115#define CONFIG_CMD_FAT
116#define CONFIG_CMD_JFFS2
117#define CONFIG_CMD_MMC
118#undef CONFIG_CMD_FPGA
119#undef CONFIG_CMD_SETGETDCR
120
Andreas Bießmannbf018332011-04-18 04:12:41 +0000121#define CONFIG_ATMEL_USART
122#define CONFIG_MACB
123#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmannbf018332011-04-18 04:12:41 +0000125#define CONFIG_SYS_HSDRAMC
126#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200127#define CONFIG_GENERIC_ATMEL_MCI
128#define CONFIG_GENERIC_MMC
129#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
Julien May5c374c92008-06-23 13:57:52 +0200130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DCACHE_LINESZ 32
132#define CONFIG_SYS_ICACHE_LINESZ 32
Julien May5c374c92008-06-23 13:57:52 +0200133
134#define CONFIG_NR_DRAM_BANKS 1
135
Andreas Bießmannbf018332011-04-18 04:12:41 +0000136#define CONFIG_SYS_FLASH_CFI
137#define CONFIG_FLASH_CFI_DRIVER
Julien May5c374c92008-06-23 13:57:52 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH_BASE 0x00000000
140#define CONFIG_SYS_FLASH_SIZE 0x800000
141#define CONFIG_SYS_MAX_FLASH_BANKS 1
142#define CONFIG_SYS_MAX_FLASH_SECT 135
Julien May5c374c92008-06-23 13:57:52 +0200143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann15cc55a2011-04-18 04:12:47 +0000145#define CONFIG_SYS_TEXT_BASE 0x00000000
Julien May5c374c92008-06-23 13:57:52 +0200146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_INTRAM_BASE 0x24000000
148#define CONFIG_SYS_INTRAM_SIZE 0x8000
Julien May5c374c92008-06-23 13:57:52 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SDRAM_BASE 0x10000000
Julien May5c374c92008-06-23 13:57:52 +0200151
Andreas Bießmannbf018332011-04-18 04:12:41 +0000152#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200153#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MALLOC_LEN (256*1024)
Julien May5c374c92008-06-23 13:57:52 +0200159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Julien May5c374c92008-06-23 13:57:52 +0200161
162/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
164#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Julien May5c374c92008-06-23 13:57:52 +0200165
166/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_PROMPT "Hammerhead> "
168#define CONFIG_SYS_CBSIZE 256
169#define CONFIG_SYS_MAXARGS 16
170#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmannbf018332011-04-18 04:12:41 +0000171#define CONFIG_SYS_LONGHELP
Julien May5c374c92008-06-23 13:57:52 +0200172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
174#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Julien May5c374c92008-06-23 13:57:52 +0200175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Julien May5c374c92008-06-23 13:57:52 +0200177
178#endif /* __CONFIG_H */