Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 1 | /* |
Scott Wood | cfcbf8c | 2009-09-02 16:45:31 -0500 | [diff] [blame] | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de |
| 4 | * Copyright 2009 Ilya Yanok, <yanok@emcraft.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 18 | * MA 02110-1301, USA. |
| 19 | */ |
| 20 | |
| 21 | #include <common.h> |
| 22 | #include <nand.h> |
| 23 | #include <linux/err.h> |
| 24 | #include <asm/io.h> |
| 25 | #ifdef CONFIG_MX27 |
| 26 | #include <asm/arch/imx-regs.h> |
| 27 | #endif |
| 28 | |
| 29 | #define DRIVER_NAME "mxc_nand" |
| 30 | |
| 31 | struct nfc_regs { |
| 32 | /* NFC RAM BUFFER Main area 0 */ |
| 33 | uint8_t main_area0[0x200]; |
| 34 | uint8_t main_area1[0x200]; |
| 35 | uint8_t main_area2[0x200]; |
| 36 | uint8_t main_area3[0x200]; |
| 37 | /* SPARE BUFFER Spare area 0 */ |
| 38 | uint8_t spare_area0[0x10]; |
| 39 | uint8_t spare_area1[0x10]; |
| 40 | uint8_t spare_area2[0x10]; |
| 41 | uint8_t spare_area3[0x10]; |
| 42 | uint8_t pad[0x5c0]; |
| 43 | /* NFC registers */ |
| 44 | uint16_t nfc_buf_size; |
| 45 | uint16_t reserved; |
| 46 | uint16_t nfc_buf_addr; |
| 47 | uint16_t nfc_flash_addr; |
| 48 | uint16_t nfc_flash_cmd; |
| 49 | uint16_t nfc_config; |
| 50 | uint16_t nfc_ecc_status_result; |
| 51 | uint16_t nfc_rsltmain_area; |
| 52 | uint16_t nfc_rsltspare_area; |
| 53 | uint16_t nfc_wrprot; |
| 54 | uint16_t nfc_unlockstart_blkaddr; |
| 55 | uint16_t nfc_unlockend_blkaddr; |
| 56 | uint16_t nfc_nf_wrprst; |
| 57 | uint16_t nfc_config1; |
| 58 | uint16_t nfc_config2; |
| 59 | }; |
| 60 | |
| 61 | /* |
| 62 | * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register |
| 63 | * for Command operation |
| 64 | */ |
| 65 | #define NFC_CMD 0x1 |
| 66 | |
| 67 | /* |
| 68 | * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register |
| 69 | * for Address operation |
| 70 | */ |
| 71 | #define NFC_ADDR 0x2 |
| 72 | |
| 73 | /* |
| 74 | * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register |
| 75 | * for Input operation |
| 76 | */ |
| 77 | #define NFC_INPUT 0x4 |
| 78 | |
| 79 | /* |
| 80 | * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register |
| 81 | * for Data Output operation |
| 82 | */ |
| 83 | #define NFC_OUTPUT 0x8 |
| 84 | |
| 85 | /* |
| 86 | * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register |
| 87 | * for Read ID operation |
| 88 | */ |
| 89 | #define NFC_ID 0x10 |
| 90 | |
| 91 | /* |
| 92 | * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register |
| 93 | * for Read Status operation |
| 94 | */ |
| 95 | #define NFC_STATUS 0x20 |
| 96 | |
| 97 | /* |
| 98 | * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read |
| 99 | * Status operation |
| 100 | */ |
| 101 | #define NFC_INT 0x8000 |
| 102 | |
| 103 | #define NFC_SP_EN (1 << 2) |
| 104 | #define NFC_ECC_EN (1 << 3) |
| 105 | #define NFC_BIG (1 << 5) |
| 106 | #define NFC_RST (1 << 6) |
| 107 | #define NFC_CE (1 << 7) |
| 108 | #define NFC_ONE_CYCLE (1 << 8) |
| 109 | |
| 110 | typedef enum {false, true} bool; |
| 111 | |
| 112 | struct mxc_nand_host { |
| 113 | struct mtd_info mtd; |
| 114 | struct nand_chip *nand; |
| 115 | |
| 116 | struct nfc_regs __iomem *regs; |
| 117 | int spare_only; |
| 118 | int status_request; |
| 119 | int pagesize_2k; |
| 120 | int clk_act; |
| 121 | uint16_t col_addr; |
| 122 | }; |
| 123 | |
| 124 | static struct mxc_nand_host mxc_host; |
| 125 | static struct mxc_nand_host *host = &mxc_host; |
| 126 | |
| 127 | /* Define delays in microsec for NAND device operations */ |
| 128 | #define TROP_US_DELAY 2000 |
| 129 | /* Macros to get byte and bit positions of ECC */ |
| 130 | #define COLPOS(x) ((x) >> 3) |
| 131 | #define BITPOS(x) ((x) & 0xf) |
| 132 | |
| 133 | /* Define single bit Error positions in Main & Spare area */ |
| 134 | #define MAIN_SINGLEBIT_ERROR 0x4 |
| 135 | #define SPARE_SINGLEBIT_ERROR 0x1 |
| 136 | |
| 137 | /* OOB placement block for use with hardware ecc generation */ |
| 138 | #ifdef CONFIG_MXC_NAND_HWECC |
| 139 | static struct nand_ecclayout nand_hw_eccoob = { |
| 140 | .eccbytes = 5, |
| 141 | .eccpos = {6, 7, 8, 9, 10}, |
| 142 | .oobfree = {{0, 5}, {11, 5}, } |
| 143 | }; |
| 144 | #else |
| 145 | static struct nand_ecclayout nand_soft_eccoob = { |
| 146 | .eccbytes = 6, |
| 147 | .eccpos = {6, 7, 8, 9, 10, 11}, |
| 148 | .oobfree = {{0, 5}, {12, 4}, } |
| 149 | }; |
| 150 | #endif |
| 151 | |
Magnus Lilja | c4832df | 2010-01-17 17:46:10 +0100 | [diff] [blame] | 152 | static struct nand_ecclayout nand_hw_eccoob_largepage = { |
| 153 | .eccbytes = 20, |
| 154 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, |
| 155 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, |
| 156 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } |
| 157 | }; |
| 158 | |
Magnus Lilja | f6a9748 | 2009-11-11 20:18:43 +0100 | [diff] [blame] | 159 | #ifdef CONFIG_MX27 |
| 160 | static int is_16bit_nand(void) |
| 161 | { |
| 162 | struct system_control_regs *sc_regs = |
| 163 | (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; |
| 164 | |
| 165 | if (readl(&sc_regs->fmcr) & NF_16BIT_SEL) |
| 166 | return 1; |
| 167 | else |
| 168 | return 0; |
| 169 | } |
| 170 | #elif defined(CONFIG_MX31) |
| 171 | static int is_16bit_nand(void) |
| 172 | { |
| 173 | struct clock_control_regs *sc_regs = |
| 174 | (struct clock_control_regs *)CCM_BASE; |
| 175 | |
| 176 | if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B) |
| 177 | return 1; |
| 178 | else |
| 179 | return 0; |
| 180 | } |
| 181 | #else |
| 182 | #warning "8/16 bit NAND autodetection not supported" |
| 183 | static int is_16bit_nand(void) |
| 184 | { |
| 185 | return 0; |
| 186 | } |
| 187 | #endif |
| 188 | |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 189 | static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size) |
| 190 | { |
| 191 | uint32_t *d = dest; |
| 192 | |
| 193 | size >>= 2; |
| 194 | while (size--) |
| 195 | __raw_writel(__raw_readl(source++), d++); |
| 196 | return dest; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * This function polls the NANDFC to wait for the basic operation to |
| 201 | * complete by checking the INT bit of config2 register. |
| 202 | */ |
| 203 | static void wait_op_done(struct mxc_nand_host *host, int max_retries, |
| 204 | uint16_t param) |
| 205 | { |
| 206 | uint32_t tmp; |
| 207 | |
| 208 | while (max_retries-- > 0) { |
| 209 | if (readw(&host->regs->nfc_config2) & NFC_INT) { |
| 210 | tmp = readw(&host->regs->nfc_config2); |
| 211 | tmp &= ~NFC_INT; |
| 212 | writew(tmp, &host->regs->nfc_config2); |
| 213 | break; |
| 214 | } |
| 215 | udelay(1); |
| 216 | } |
| 217 | if (max_retries < 0) { |
| 218 | MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", |
| 219 | __func__, param); |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * This function issues the specified command to the NAND device and |
| 225 | * waits for completion. |
| 226 | */ |
| 227 | static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) |
| 228 | { |
| 229 | MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); |
| 230 | |
| 231 | writew(cmd, &host->regs->nfc_flash_cmd); |
| 232 | writew(NFC_CMD, &host->regs->nfc_config2); |
| 233 | |
| 234 | /* Wait for operation to complete */ |
| 235 | wait_op_done(host, TROP_US_DELAY, cmd); |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * This function sends an address (or partial address) to the |
| 240 | * NAND device. The address is used to select the source/destination for |
| 241 | * a NAND command. |
| 242 | */ |
| 243 | static void send_addr(struct mxc_nand_host *host, uint16_t addr) |
| 244 | { |
| 245 | MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); |
| 246 | |
| 247 | writew(addr, &host->regs->nfc_flash_addr); |
| 248 | writew(NFC_ADDR, &host->regs->nfc_config2); |
| 249 | |
| 250 | /* Wait for operation to complete */ |
| 251 | wait_op_done(host, TROP_US_DELAY, addr); |
| 252 | } |
| 253 | |
| 254 | /* |
| 255 | * This function requests the NANDFC to initate the transfer |
| 256 | * of data currently in the NANDFC RAM buffer to the NAND device. |
| 257 | */ |
| 258 | static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, |
| 259 | int spare_only) |
| 260 | { |
| 261 | MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only); |
| 262 | |
| 263 | writew(buf_id, &host->regs->nfc_buf_addr); |
| 264 | |
| 265 | /* Configure spare or page+spare access */ |
| 266 | if (!host->pagesize_2k) { |
| 267 | uint16_t config1 = readw(&host->regs->nfc_config1); |
| 268 | if (spare_only) |
| 269 | config1 |= NFC_SP_EN; |
| 270 | else |
| 271 | config1 &= ~(NFC_SP_EN); |
| 272 | writew(config1, &host->regs->nfc_config1); |
| 273 | } |
| 274 | |
| 275 | writew(NFC_INPUT, &host->regs->nfc_config2); |
| 276 | |
| 277 | /* Wait for operation to complete */ |
| 278 | wait_op_done(host, TROP_US_DELAY, spare_only); |
| 279 | } |
| 280 | |
| 281 | /* |
| 282 | * Requests NANDFC to initated the transfer of data from the |
| 283 | * NAND device into in the NANDFC ram buffer. |
| 284 | */ |
| 285 | static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, |
| 286 | int spare_only) |
| 287 | { |
| 288 | MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); |
| 289 | |
| 290 | writew(buf_id, &host->regs->nfc_buf_addr); |
| 291 | |
| 292 | /* Configure spare or page+spare access */ |
| 293 | if (!host->pagesize_2k) { |
| 294 | uint32_t config1 = readw(&host->regs->nfc_config1); |
| 295 | if (spare_only) |
| 296 | config1 |= NFC_SP_EN; |
| 297 | else |
| 298 | config1 &= ~NFC_SP_EN; |
| 299 | writew(config1, &host->regs->nfc_config1); |
| 300 | } |
| 301 | |
| 302 | writew(NFC_OUTPUT, &host->regs->nfc_config2); |
| 303 | |
| 304 | /* Wait for operation to complete */ |
| 305 | wait_op_done(host, TROP_US_DELAY, spare_only); |
| 306 | } |
| 307 | |
| 308 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
| 309 | static void send_read_id(struct mxc_nand_host *host) |
| 310 | { |
| 311 | uint16_t tmp; |
| 312 | |
| 313 | /* NANDFC buffer 0 is used for device ID output */ |
| 314 | writew(0x0, &host->regs->nfc_buf_addr); |
| 315 | |
| 316 | /* Read ID into main buffer */ |
| 317 | tmp = readw(&host->regs->nfc_config1); |
| 318 | tmp &= ~NFC_SP_EN; |
| 319 | writew(tmp, &host->regs->nfc_config1); |
| 320 | |
| 321 | writew(NFC_ID, &host->regs->nfc_config2); |
| 322 | |
| 323 | /* Wait for operation to complete */ |
| 324 | wait_op_done(host, TROP_US_DELAY, 0); |
| 325 | } |
| 326 | |
| 327 | /* |
| 328 | * This function requests the NANDFC to perform a read of the |
| 329 | * NAND device status and returns the current status. |
| 330 | */ |
| 331 | static uint16_t get_dev_status(struct mxc_nand_host *host) |
| 332 | { |
| 333 | void __iomem *main_buf = host->regs->main_area1; |
| 334 | uint32_t store; |
| 335 | uint16_t ret, tmp; |
| 336 | /* Issue status request to NAND device */ |
| 337 | |
| 338 | /* store the main area1 first word, later do recovery */ |
| 339 | store = readl(main_buf); |
| 340 | /* NANDFC buffer 1 is used for device status */ |
| 341 | writew(1, &host->regs->nfc_buf_addr); |
| 342 | |
| 343 | /* Read status into main buffer */ |
| 344 | tmp = readw(&host->regs->nfc_config1); |
| 345 | tmp &= ~NFC_SP_EN; |
| 346 | writew(tmp, &host->regs->nfc_config1); |
| 347 | |
| 348 | writew(NFC_STATUS, &host->regs->nfc_config2); |
| 349 | |
| 350 | /* Wait for operation to complete */ |
| 351 | wait_op_done(host, TROP_US_DELAY, 0); |
| 352 | |
| 353 | /* |
| 354 | * Status is placed in first word of main buffer |
| 355 | * get status, then recovery area 1 data |
| 356 | */ |
| 357 | ret = readw(main_buf); |
| 358 | writel(store, main_buf); |
| 359 | |
| 360 | return ret; |
| 361 | } |
| 362 | |
| 363 | /* This function is used by upper layer to checks if device is ready */ |
| 364 | static int mxc_nand_dev_ready(struct mtd_info *mtd) |
| 365 | { |
| 366 | /* |
| 367 | * NFC handles R/B internally. Therefore, this function |
| 368 | * always returns status as ready. |
| 369 | */ |
| 370 | return 1; |
| 371 | } |
| 372 | |
| 373 | #ifdef CONFIG_MXC_NAND_HWECC |
| 374 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 375 | { |
| 376 | /* |
| 377 | * If HW ECC is enabled, we turn it on during init. There is |
| 378 | * no need to enable again here. |
| 379 | */ |
| 380 | } |
| 381 | |
| 382 | static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
| 383 | u_char *read_ecc, u_char *calc_ecc) |
| 384 | { |
| 385 | struct nand_chip *nand_chip = mtd->priv; |
| 386 | struct mxc_nand_host *host = nand_chip->priv; |
| 387 | |
| 388 | /* |
| 389 | * 1-Bit errors are automatically corrected in HW. No need for |
| 390 | * additional correction. 2-Bit errors cannot be corrected by |
| 391 | * HW ECC, so we need to return failure |
| 392 | */ |
| 393 | uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result); |
| 394 | |
| 395 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { |
| 396 | MTDDEBUG(MTD_DEBUG_LEVEL0, |
| 397 | "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
| 398 | return -1; |
| 399 | } |
| 400 | |
| 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 405 | u_char *ecc_code) |
| 406 | { |
| 407 | return 0; |
| 408 | } |
| 409 | #endif |
| 410 | |
| 411 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) |
| 412 | { |
| 413 | struct nand_chip *nand_chip = mtd->priv; |
| 414 | struct mxc_nand_host *host = nand_chip->priv; |
| 415 | uint8_t ret = 0; |
| 416 | uint16_t col; |
| 417 | uint16_t __iomem *main_buf = |
| 418 | (uint16_t __iomem *)host->regs->main_area0; |
| 419 | uint16_t __iomem *spare_buf = |
| 420 | (uint16_t __iomem *)host->regs->spare_area0; |
| 421 | union { |
| 422 | uint16_t word; |
| 423 | uint8_t bytes[2]; |
| 424 | } nfc_word; |
| 425 | |
| 426 | /* Check for status request */ |
| 427 | if (host->status_request) |
| 428 | return get_dev_status(host) & 0xFF; |
| 429 | |
| 430 | /* Get column for 16-bit access */ |
| 431 | col = host->col_addr >> 1; |
| 432 | |
| 433 | /* If we are accessing the spare region */ |
| 434 | if (host->spare_only) |
| 435 | nfc_word.word = readw(&spare_buf[col]); |
| 436 | else |
| 437 | nfc_word.word = readw(&main_buf[col]); |
| 438 | |
| 439 | /* Pick upper/lower byte of word from RAM buffer */ |
| 440 | ret = nfc_word.bytes[host->col_addr & 0x1]; |
| 441 | |
| 442 | /* Update saved column address */ |
| 443 | if (nand_chip->options & NAND_BUSWIDTH_16) |
| 444 | host->col_addr += 2; |
| 445 | else |
| 446 | host->col_addr++; |
| 447 | |
| 448 | return ret; |
| 449 | } |
| 450 | |
| 451 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) |
| 452 | { |
| 453 | struct nand_chip *nand_chip = mtd->priv; |
| 454 | struct mxc_nand_host *host = nand_chip->priv; |
| 455 | uint16_t col, ret; |
| 456 | uint16_t __iomem *p; |
| 457 | |
| 458 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 459 | "mxc_nand_read_word(col = %d)\n", host->col_addr); |
| 460 | |
| 461 | col = host->col_addr; |
| 462 | /* Adjust saved column address */ |
| 463 | if (col < mtd->writesize && host->spare_only) |
| 464 | col += mtd->writesize; |
| 465 | |
| 466 | if (col < mtd->writesize) { |
| 467 | p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1)); |
| 468 | } else { |
| 469 | p = (uint16_t __iomem *)(host->regs->spare_area0 + |
| 470 | ((col - mtd->writesize) >> 1)); |
| 471 | } |
| 472 | |
| 473 | if (col & 1) { |
| 474 | union { |
| 475 | uint16_t word; |
| 476 | uint8_t bytes[2]; |
| 477 | } nfc_word[3]; |
| 478 | |
| 479 | nfc_word[0].word = readw(p); |
| 480 | nfc_word[1].word = readw(p + 1); |
| 481 | |
| 482 | nfc_word[2].bytes[0] = nfc_word[0].bytes[1]; |
| 483 | nfc_word[2].bytes[1] = nfc_word[1].bytes[0]; |
| 484 | |
| 485 | ret = nfc_word[2].word; |
| 486 | } else { |
| 487 | ret = readw(p); |
| 488 | } |
| 489 | |
| 490 | /* Update saved column address */ |
| 491 | host->col_addr = col + 2; |
| 492 | |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | /* |
| 497 | * Write data of length len to buffer buf. The data to be |
| 498 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input |
| 499 | * Operation by the NFC, the data is written to NAND Flash |
| 500 | */ |
| 501 | static void mxc_nand_write_buf(struct mtd_info *mtd, |
| 502 | const u_char *buf, int len) |
| 503 | { |
| 504 | struct nand_chip *nand_chip = mtd->priv; |
| 505 | struct mxc_nand_host *host = nand_chip->priv; |
| 506 | int n, col, i = 0; |
| 507 | |
| 508 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 509 | "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr, |
| 510 | len); |
| 511 | |
| 512 | col = host->col_addr; |
| 513 | |
| 514 | /* Adjust saved column address */ |
| 515 | if (col < mtd->writesize && host->spare_only) |
| 516 | col += mtd->writesize; |
| 517 | |
| 518 | n = mtd->writesize + mtd->oobsize - col; |
| 519 | n = min(len, n); |
| 520 | |
| 521 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 522 | "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n); |
| 523 | |
| 524 | while (n > 0) { |
| 525 | void __iomem *p; |
| 526 | |
| 527 | if (col < mtd->writesize) { |
| 528 | p = host->regs->main_area0 + (col & ~3); |
| 529 | } else { |
| 530 | p = host->regs->spare_area0 - |
| 531 | mtd->writesize + (col & ~3); |
| 532 | } |
| 533 | |
| 534 | MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__, |
| 535 | __LINE__, p); |
| 536 | |
| 537 | if (((col | (unsigned long)&buf[i]) & 3) || n < 4) { |
| 538 | union { |
| 539 | uint32_t word; |
| 540 | uint8_t bytes[4]; |
| 541 | } nfc_word; |
| 542 | |
| 543 | nfc_word.word = readl(p); |
| 544 | nfc_word.bytes[col & 3] = buf[i++]; |
| 545 | n--; |
| 546 | col++; |
| 547 | |
| 548 | writel(nfc_word.word, p); |
| 549 | } else { |
| 550 | int m = mtd->writesize - col; |
| 551 | |
| 552 | if (col >= mtd->writesize) |
| 553 | m += mtd->oobsize; |
| 554 | |
| 555 | m = min(n, m) & ~3; |
| 556 | |
| 557 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 558 | "%s:%d: n = %d, m = %d, i = %d, col = %d\n", |
| 559 | __func__, __LINE__, n, m, i, col); |
| 560 | |
| 561 | mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m); |
| 562 | col += m; |
| 563 | i += m; |
| 564 | n -= m; |
| 565 | } |
| 566 | } |
| 567 | /* Update saved column address */ |
| 568 | host->col_addr = col; |
| 569 | } |
| 570 | |
| 571 | /* |
| 572 | * Read the data buffer from the NAND Flash. To read the data from NAND |
| 573 | * Flash first the data output cycle is initiated by the NFC, which copies |
| 574 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. |
| 575 | */ |
| 576 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 577 | { |
| 578 | struct nand_chip *nand_chip = mtd->priv; |
| 579 | struct mxc_nand_host *host = nand_chip->priv; |
| 580 | int n, col, i = 0; |
| 581 | |
| 582 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 583 | "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len); |
| 584 | |
| 585 | col = host->col_addr; |
| 586 | |
| 587 | /* Adjust saved column address */ |
| 588 | if (col < mtd->writesize && host->spare_only) |
| 589 | col += mtd->writesize; |
| 590 | |
| 591 | n = mtd->writesize + mtd->oobsize - col; |
| 592 | n = min(len, n); |
| 593 | |
| 594 | while (n > 0) { |
| 595 | void __iomem *p; |
| 596 | |
| 597 | if (col < mtd->writesize) { |
| 598 | p = host->regs->main_area0 + (col & ~3); |
| 599 | } else { |
| 600 | p = host->regs->spare_area0 - |
| 601 | mtd->writesize + (col & ~3); |
| 602 | } |
| 603 | |
| 604 | if (((col | (int)&buf[i]) & 3) || n < 4) { |
| 605 | union { |
| 606 | uint32_t word; |
| 607 | uint8_t bytes[4]; |
| 608 | } nfc_word; |
| 609 | |
| 610 | nfc_word.word = readl(p); |
| 611 | buf[i++] = nfc_word.bytes[col & 3]; |
| 612 | n--; |
| 613 | col++; |
| 614 | } else { |
| 615 | int m = mtd->writesize - col; |
| 616 | |
| 617 | if (col >= mtd->writesize) |
| 618 | m += mtd->oobsize; |
| 619 | |
| 620 | m = min(n, m) & ~3; |
| 621 | mxc_nand_memcpy32((uint32_t *)&buf[i], p, m); |
| 622 | |
| 623 | col += m; |
| 624 | i += m; |
| 625 | n -= m; |
| 626 | } |
| 627 | } |
| 628 | /* Update saved column address */ |
| 629 | host->col_addr = col; |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * Used by the upper layer to verify the data in NAND Flash |
| 634 | * with the data in the buf. |
| 635 | */ |
| 636 | static int mxc_nand_verify_buf(struct mtd_info *mtd, |
| 637 | const u_char *buf, int len) |
| 638 | { |
| 639 | u_char tmp[256]; |
| 640 | uint bsize; |
| 641 | |
| 642 | while (len) { |
| 643 | bsize = min(len, 256); |
| 644 | mxc_nand_read_buf(mtd, tmp, bsize); |
| 645 | |
| 646 | if (memcmp(buf, tmp, bsize)) |
| 647 | return 1; |
| 648 | |
| 649 | buf += bsize; |
| 650 | len -= bsize; |
| 651 | } |
| 652 | |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | /* |
| 657 | * This function is used by upper layer for select and |
| 658 | * deselect of the NAND chip |
| 659 | */ |
| 660 | static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) |
| 661 | { |
| 662 | struct nand_chip *nand_chip = mtd->priv; |
| 663 | struct mxc_nand_host *host = nand_chip->priv; |
| 664 | |
| 665 | switch (chip) { |
| 666 | case -1: |
| 667 | /* TODO: Disable the NFC clock */ |
| 668 | if (host->clk_act) |
| 669 | host->clk_act = 0; |
| 670 | break; |
| 671 | case 0: |
| 672 | /* TODO: Enable the NFC clock */ |
| 673 | if (!host->clk_act) |
| 674 | host->clk_act = 1; |
| 675 | break; |
| 676 | |
| 677 | default: |
| 678 | break; |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | /* |
| 683 | * Used by the upper layer to write command to NAND Flash for |
| 684 | * different operations to be carried out on NAND Flash |
| 685 | */ |
| 686 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, |
| 687 | int column, int page_addr) |
| 688 | { |
| 689 | struct nand_chip *nand_chip = mtd->priv; |
| 690 | struct mxc_nand_host *host = nand_chip->priv; |
| 691 | |
| 692 | MTDDEBUG(MTD_DEBUG_LEVEL3, |
| 693 | "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
| 694 | command, column, page_addr); |
| 695 | |
| 696 | /* Reset command state information */ |
| 697 | host->status_request = false; |
| 698 | |
| 699 | /* Command pre-processing step */ |
| 700 | switch (command) { |
| 701 | |
| 702 | case NAND_CMD_STATUS: |
| 703 | host->col_addr = 0; |
| 704 | host->status_request = true; |
| 705 | break; |
| 706 | |
| 707 | case NAND_CMD_READ0: |
| 708 | host->col_addr = column; |
| 709 | host->spare_only = false; |
| 710 | break; |
| 711 | |
| 712 | case NAND_CMD_READOOB: |
| 713 | host->col_addr = column; |
| 714 | host->spare_only = true; |
| 715 | if (host->pagesize_2k) |
| 716 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
| 717 | break; |
| 718 | |
| 719 | case NAND_CMD_SEQIN: |
| 720 | if (column >= mtd->writesize) { |
| 721 | /* |
| 722 | * before sending SEQIN command for partial write, |
| 723 | * we need read one page out. FSL NFC does not support |
| 724 | * partial write. It alway send out 512+ecc+512+ecc ... |
| 725 | * for large page nand flash. But for small page nand |
| 726 | * flash, it does support SPARE ONLY operation. |
| 727 | */ |
| 728 | if (host->pagesize_2k) { |
| 729 | /* call ourself to read a page */ |
| 730 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, |
| 731 | page_addr); |
| 732 | } |
| 733 | |
| 734 | host->col_addr = column - mtd->writesize; |
| 735 | host->spare_only = true; |
| 736 | |
| 737 | /* Set program pointer to spare region */ |
| 738 | if (!host->pagesize_2k) |
| 739 | send_cmd(host, NAND_CMD_READOOB); |
| 740 | } else { |
| 741 | host->spare_only = false; |
| 742 | host->col_addr = column; |
| 743 | |
| 744 | /* Set program pointer to page start */ |
| 745 | if (!host->pagesize_2k) |
| 746 | send_cmd(host, NAND_CMD_READ0); |
| 747 | } |
| 748 | break; |
| 749 | |
| 750 | case NAND_CMD_PAGEPROG: |
| 751 | send_prog_page(host, 0, host->spare_only); |
| 752 | |
| 753 | if (host->pagesize_2k) { |
| 754 | /* data in 4 areas datas */ |
| 755 | send_prog_page(host, 1, host->spare_only); |
| 756 | send_prog_page(host, 2, host->spare_only); |
| 757 | send_prog_page(host, 3, host->spare_only); |
| 758 | } |
| 759 | |
| 760 | break; |
| 761 | } |
| 762 | |
| 763 | /* Write out the command to the device. */ |
| 764 | send_cmd(host, command); |
| 765 | |
| 766 | /* Write out column address, if necessary */ |
| 767 | if (column != -1) { |
| 768 | /* |
| 769 | * MXC NANDFC can only perform full page+spare or |
| 770 | * spare-only read/write. When the upper layers |
| 771 | * layers perform a read/write buf operation, |
| 772 | * we will used the saved column adress to index into |
| 773 | * the full page. |
| 774 | */ |
| 775 | send_addr(host, 0); |
| 776 | if (host->pagesize_2k) |
| 777 | /* another col addr cycle for 2k page */ |
| 778 | send_addr(host, 0); |
| 779 | } |
| 780 | |
| 781 | /* Write out page address, if necessary */ |
| 782 | if (page_addr != -1) { |
| 783 | /* paddr_0 - p_addr_7 */ |
| 784 | send_addr(host, (page_addr & 0xff)); |
| 785 | |
| 786 | if (host->pagesize_2k) { |
| 787 | send_addr(host, (page_addr >> 8) & 0xFF); |
| 788 | if (mtd->size >= 0x10000000) { |
| 789 | /* paddr_8 - paddr_15 */ |
| 790 | send_addr(host, (page_addr >> 8) & 0xff); |
| 791 | send_addr(host, (page_addr >> 16) & 0xff); |
| 792 | } else { |
| 793 | /* paddr_8 - paddr_15 */ |
| 794 | send_addr(host, (page_addr >> 8) & 0xff); |
| 795 | } |
| 796 | } else { |
| 797 | /* One more address cycle for higher density devices */ |
| 798 | if (mtd->size >= 0x4000000) { |
| 799 | /* paddr_8 - paddr_15 */ |
| 800 | send_addr(host, (page_addr >> 8) & 0xff); |
| 801 | send_addr(host, (page_addr >> 16) & 0xff); |
| 802 | } else { |
| 803 | /* paddr_8 - paddr_15 */ |
| 804 | send_addr(host, (page_addr >> 8) & 0xff); |
| 805 | } |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | /* Command post-processing step */ |
| 810 | switch (command) { |
| 811 | |
| 812 | case NAND_CMD_RESET: |
| 813 | break; |
| 814 | |
| 815 | case NAND_CMD_READOOB: |
| 816 | case NAND_CMD_READ0: |
| 817 | if (host->pagesize_2k) { |
| 818 | /* send read confirm command */ |
| 819 | send_cmd(host, NAND_CMD_READSTART); |
| 820 | /* read for each AREA */ |
| 821 | send_read_page(host, 0, host->spare_only); |
| 822 | send_read_page(host, 1, host->spare_only); |
| 823 | send_read_page(host, 2, host->spare_only); |
| 824 | send_read_page(host, 3, host->spare_only); |
| 825 | } else { |
| 826 | send_read_page(host, 0, host->spare_only); |
| 827 | } |
| 828 | break; |
| 829 | |
| 830 | case NAND_CMD_READID: |
| 831 | host->col_addr = 0; |
| 832 | send_read_id(host); |
| 833 | break; |
| 834 | |
| 835 | case NAND_CMD_PAGEPROG: |
| 836 | break; |
| 837 | |
| 838 | case NAND_CMD_STATUS: |
| 839 | break; |
| 840 | |
| 841 | case NAND_CMD_ERASE2: |
| 842 | break; |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | int board_nand_init(struct nand_chip *this) |
| 847 | { |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 848 | struct mtd_info *mtd; |
| 849 | uint16_t tmp; |
| 850 | int err = 0; |
| 851 | |
| 852 | /* structures must be linked */ |
| 853 | mtd = &host->mtd; |
| 854 | mtd->priv = this; |
| 855 | host->nand = this; |
| 856 | |
| 857 | /* 5 us command delay time */ |
| 858 | this->chip_delay = 5; |
| 859 | |
| 860 | this->priv = host; |
| 861 | this->dev_ready = mxc_nand_dev_ready; |
| 862 | this->cmdfunc = mxc_nand_command; |
| 863 | this->select_chip = mxc_nand_select_chip; |
| 864 | this->read_byte = mxc_nand_read_byte; |
| 865 | this->read_word = mxc_nand_read_word; |
| 866 | this->write_buf = mxc_nand_write_buf; |
| 867 | this->read_buf = mxc_nand_read_buf; |
| 868 | this->verify_buf = mxc_nand_verify_buf; |
| 869 | |
| 870 | host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; |
| 871 | host->clk_act = 1; |
| 872 | |
| 873 | #ifdef CONFIG_MXC_NAND_HWECC |
| 874 | this->ecc.calculate = mxc_nand_calculate_ecc; |
| 875 | this->ecc.hwctl = mxc_nand_enable_hwecc; |
| 876 | this->ecc.correct = mxc_nand_correct_data; |
| 877 | this->ecc.mode = NAND_ECC_HW; |
| 878 | this->ecc.size = 512; |
| 879 | this->ecc.bytes = 3; |
| 880 | this->ecc.layout = &nand_hw_eccoob; |
| 881 | tmp = readw(&host->regs->nfc_config1); |
| 882 | tmp |= NFC_ECC_EN; |
| 883 | writew(tmp, &host->regs->nfc_config1); |
| 884 | #else |
| 885 | this->ecc.layout = &nand_soft_eccoob; |
| 886 | this->ecc.mode = NAND_ECC_SOFT; |
| 887 | tmp = readw(&host->regs->nfc_config1); |
| 888 | tmp &= ~NFC_ECC_EN; |
| 889 | writew(tmp, &host->regs->nfc_config1); |
| 890 | #endif |
| 891 | |
| 892 | /* Reset NAND */ |
| 893 | this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
| 894 | |
| 895 | /* |
| 896 | * preset operation |
| 897 | * Unlock the internal RAM Buffer |
| 898 | */ |
| 899 | writew(0x2, &host->regs->nfc_config); |
| 900 | |
| 901 | /* Blocks to be unlocked */ |
| 902 | writew(0x0, &host->regs->nfc_unlockstart_blkaddr); |
| 903 | writew(0x4000, &host->regs->nfc_unlockend_blkaddr); |
| 904 | |
| 905 | /* Unlock Block Command for given address range */ |
| 906 | writew(0x4, &host->regs->nfc_wrprot); |
| 907 | |
| 908 | /* NAND bus width determines access funtions used by upper layer */ |
Magnus Lilja | f6a9748 | 2009-11-11 20:18:43 +0100 | [diff] [blame] | 909 | if (is_16bit_nand()) |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 910 | this->options |= NAND_BUSWIDTH_16; |
| 911 | |
Magnus Lilja | c4832df | 2010-01-17 17:46:10 +0100 | [diff] [blame] | 912 | #ifdef CONFIG_SYS_NAND_LARGEPAGE |
| 913 | host->pagesize_2k = 1; |
| 914 | this->ecc.layout = &nand_hw_eccoob_largepage; |
| 915 | #else |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 916 | host->pagesize_2k = 0; |
Magnus Lilja | c4832df | 2010-01-17 17:46:10 +0100 | [diff] [blame] | 917 | #endif |
Ilya Yanok | 36fab99 | 2009-08-11 02:32:54 +0400 | [diff] [blame] | 918 | |
| 919 | return err; |
| 920 | } |