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Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09001/*
2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3 * Copyright (C) 2012 Renesas Solutions Corp.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09006 */
7
8#ifndef __KZM9G_H
9#define __KZM9G_H
10
11#undef DEBUG
12
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090013#define CONFIG_SH73A0
14#define CONFIG_KZM_A9_GT
15#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
16#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
Tetsuyuki Kobayashifc56da02014-04-14 17:13:58 +090017#define CONFIG_SYS_GENERIC_BOARD
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090018
19#include <asm/arch/rmobile.h>
20
21#define CONFIG_ARCH_CPU_INIT
22#define CONFIG_DISPLAY_CPUINFO
23#define CONFIG_DISPLAY_BOARDINFO
24#define CONFIG_BOARD_EARLY_INIT_F
Nobuhiro Iwamatsu15f2aa72012-07-27 11:40:13 +090025#define CONFIG_OF_LIBFDT
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090026
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090027#define CONFIG_CMDLINE_TAG
28#define CONFIG_SETUP_MEMORY_TAGS
29#define CONFIG_INITRD_TAG
30#define CONFIG_DOS_PARTITION
31#define CONFIG_CMD_FAT
32#define CONFIG_CMD_BOOTZ
33
Tetsuyuki Kobayashi18a65af2012-07-19 16:16:08 +000034#define CONFIG_BAUDRATE 115200
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090035#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090036#define CONFIG_BOOTDELAY 3
37
38#define CONFIG_VERSION_VARIABLE
39#undef CONFIG_SHOW_BOOT_PROGRESS
40
41/* MEMORY */
42#define KZM_SDRAM_BASE (0x40000000)
43#define PHYS_SDRAM KZM_SDRAM_BASE
44#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
45#define CONFIG_NR_DRAM_BANKS (1)
46
47/* NOR Flash */
48#define KZM_FLASH_BASE (0x00000000)
49#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
50#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
51#define CONFIG_SYS_MAX_FLASH_BANKS (1)
52#define CONFIG_SYS_MAX_FLASH_SECT (512)
53
54/* prompt */
55#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090056#define CONFIG_SYS_CBSIZE 256
57#define CONFIG_SYS_PBSIZE 256
58#define CONFIG_SYS_MAXARGS 16
59#define CONFIG_SYS_BARGSIZE 512
60#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
61
62/* SCIF */
63#define CONFIG_SCIF_CONSOLE
64#define CONFIG_CONS_SCIF4
65#undef CONFIG_SYS_CONSOLE_INFO_QUIET
66#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
67#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
68
69#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
70#define CONFIG_SYS_MEMTEST_END \
71 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
72#undef CONFIG_SYS_ALT_MEMTEST
73#undef CONFIG_SYS_MEMTEST_SCRATCH
74#undef CONFIG_SYS_LOADS_BAUD_CHANGE
75
76#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
77#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
78#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
79#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
80 CONFIG_SYS_INIT_RAM_SIZE - \
81 GENERATED_GBL_DATA_SIZE)
Tetsuyuki Kobayashi9415cf92012-07-05 01:43:44 +000082#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
83#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
84#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090085#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
86
87#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
88#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090089#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
90
91#define CONFIG_SYS_TEXT_BASE 0x00000000
92#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
93
94/* FLASH */
95#define CONFIG_FLASH_CFI_DRIVER
96#define CONFIG_SYS_FLASH_CFI
97#undef CONFIG_SYS_FLASH_QUIET_TEST
98#define CONFIG_SYS_FLASH_EMPTY_INFO
99#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
100#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
101#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
102#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
103
104/* Timeout for Flash erase operations (in ms) */
105#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
106/* Timeout for Flash write operations (in ms) */
107#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
108/* Timeout for Flash set sector lock bit operations (in ms) */
109#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
110/* Timeout for Flash clear lock bit operations (in ms) */
111#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
112
113#undef CONFIG_SYS_FLASH_PROTECTION
114#undef CONFIG_SYS_DIRECT_FLASH_TFTP
115#define CONFIG_ENV_IS_IN_FLASH
116
117/* GPIO / PFC */
118#define CONFIG_SH_GPIO_PFC
119
120/* Clock */
Nobuhiro Iwamatsueae6c8a2012-08-03 13:56:52 +0900121#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900122#define CONFIG_SYS_CLK_FREQ (48000000)
123#define CONFIG_SYS_CPU_CLK (1196000000)
Nobuhiro Iwamatsu59562ff2013-09-30 10:30:40 +0900124#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900125#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900126
127/* Ether */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900128#define CONFIG_CMD_PING
129#define CONFIG_CMD_DHCP
130#define CONFIG_SMC911X
131#define CONFIG_SMC911X_BASE (0x10000000)
132#define CONFIG_SMC911X_32_BIT
Tetsuyuki Kobayashi38263df2012-07-25 18:24:18 +0000133#define CONFIG_NFS_TIMEOUT 10000UL
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900134
135/* I2C */
136#define CONFIG_CMD_I2C
Nobuhiro Iwamatsu2035d772013-10-29 13:33:51 +0900137#define CONFIG_SYS_I2C
138#define CONFIG_SYS_I2C_SH
139#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
140#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
141#define CONFIG_SYS_I2C_SH_SPEED0 100000
142#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
143#define CONFIG_SYS_I2C_SH_SPEED1 100000
144#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
145#define CONFIG_SYS_I2C_SH_SPEED2 100000
146#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
147#define CONFIG_SYS_I2C_SH_SPEED3 100000
148#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
149#define CONFIG_SYS_I2C_SH_SPEED4 100000
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000150#define CONFIG_SH_I2C_8BIT
Nobuhiro Iwamatsu2035d772013-10-29 13:33:51 +0900151#define CONFIG_SH_I2C_DATA_HIGH 4
152#define CONFIG_SH_I2C_DATA_LOW 5
153#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900154
155#endif /* __KZM9G_H */