blob: 8e57e860f25eb7ad74d375a6aac0aff0a54b8ad1 [file] [log] [blame]
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +05301// SPDX-License-Identifier: GPL-2.0
2/*
Suman Anna066e8602023-08-02 13:47:24 +05303 * Copyright (C) 2019-2023 Texas Instruments Incorporated - https://www.ti.com
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +05304 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7#include <linux/kernel.h>
8
9#include "k3-psil-priv.h"
10
11#define PSIL_ETHERNET(x) \
12 { \
13 .thread_id = x, \
14 .ep_config = { \
15 .ep_type = PSIL_EP_NATIVE, \
16 .pkt_mode = 1, \
17 .needs_epib = 1, \
18 .psd_size = 16, \
19 }, \
20 }
21
22/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
23static struct psil_ep j721e_src_ep_map[] = {
Suman Anna066e8602023-08-02 13:47:24 +053024 /* MCU_CPSW0 */
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +053025 PSIL_ETHERNET(0x7000),
Suman Anna066e8602023-08-02 13:47:24 +053026 /* MAIN_CPSW0 */
27 PSIL_ETHERNET(0x4a00),
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +053028};
29
30/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
31static struct psil_ep j721e_dst_ep_map[] = {
Suman Anna066e8602023-08-02 13:47:24 +053032 /* MCU_CPSW0 */
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +053033 PSIL_ETHERNET(0xf000),
34 PSIL_ETHERNET(0xf001),
35 PSIL_ETHERNET(0xf002),
36 PSIL_ETHERNET(0xf003),
37 PSIL_ETHERNET(0xf004),
38 PSIL_ETHERNET(0xf005),
39 PSIL_ETHERNET(0xf006),
40 PSIL_ETHERNET(0xf007),
Suman Anna066e8602023-08-02 13:47:24 +053041 /* MAIN_CPSW0 */
42 PSIL_ETHERNET(0xca00),
43 PSIL_ETHERNET(0xca01),
44 PSIL_ETHERNET(0xca02),
45 PSIL_ETHERNET(0xca03),
46 PSIL_ETHERNET(0xca04),
47 PSIL_ETHERNET(0xca05),
48 PSIL_ETHERNET(0xca06),
49 PSIL_ETHERNET(0xca07),
Vignesh Raghavendra53b04c62020-07-07 13:43:33 +053050};
51
52struct psil_ep_map j721e_ep_map = {
53 .name = "j721e",
54 .src = j721e_src_ep_map,
55 .src_count = ARRAY_SIZE(j721e_src_ep_map),
56 .dst = j721e_dst_ep_map,
57 .dst_count = ARRAY_SIZE(j721e_dst_ep_map),
58};