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Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05301/*
2 * Xilinx MicroZED board DTS
3 *
Michal Simek371fc582016-01-12 08:06:36 +01004 * Copyright (C) 2013 - 2016 Xilinx, Inc.
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05305 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
12 model = "Zynq MicroZED Board";
13 compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090014
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090015 aliases {
16 serial0 = &uart1;
Jagan Teki659cc152015-08-15 23:08:51 +053017 spi0 = &qspi;
Michal Simek371fc582016-01-12 08:06:36 +010018 mmc0 = &sdhci0;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090019 };
20
Michal Simekcc7978b2016-11-11 13:11:37 +010021 memory@0 {
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090022 device_type = "memory";
23 reg = <0 0x40000000>;
24 };
Michal Simek371fc582016-01-12 08:06:36 +010025
26 chosen {
27 bootargs = "earlyprintk";
28 stdout-path = "serial0:115200n8";
29 };
30
31 usb_phy0: phy0 {
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
34 };
35};
36
37&clkc {
38 ps-clk-frequency = <33333333>;
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053039};
Jagan Teki659cc152015-08-15 23:08:51 +053040
41&qspi {
Nathan Rossicb204a62016-02-16 23:05:03 +100042 u-boot,dm-pre-reloc;
Jagan Teki659cc152015-08-15 23:08:51 +053043 status = "okay";
44};
Simon Glass035c6b22015-10-17 19:41:24 -060045
46&uart1 {
47 u-boot,dm-pre-reloc;
48 status = "okay";
49};
Michal Simek371fc582016-01-12 08:06:36 +010050
51&gem0 {
52 status = "okay";
53 phy-mode = "rgmii-id";
54 phy-handle = <&ethernet_phy>;
55
56 ethernet_phy: ethernet-phy@0 {
57 reg = <0>;
58 };
59};
60
61&sdhci0 {
62 u-boot,dm-pre-reloc;
63 status = "okay";
64};
65
66&usb0 {
67 status = "okay";
68 dr_mode = "host";
69 usb-phy = <&usb_phy0>;
70};