blob: 276428f4df3a942c38b31a286414b521db8b0180 [file] [log] [blame]
York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7/*
8 * T4240 QDS board configuration file
9 */
York Sun1cb19fb2013-06-27 10:48:29 -070010#ifndef __CONFIG_H
11#define __CONFIG_H
12
York Sunee52b182012-10-11 07:13:37 +000013#define CONFIG_T4240QDS
14#define CONFIG_PHYS_64BIT
York Sunee52b182012-10-11 07:13:37 +000015
16#define CONFIG_FSL_SATA_V2
17#define CONFIG_PCIE4
Ruchika Gupta737537e2014-10-15 11:35:31 +053018#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
York Sunee52b182012-10-11 07:13:37 +000019
20#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
21
York Sun1cb19fb2013-06-27 10:48:29 -070022#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090023#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
24#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
Shaohui Xieb6036992014-04-22 15:10:44 +080025#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28#else
Shaohui Xieb6036992014-04-22 15:10:44 +080029#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
30#define CONFIG_SPL_ENV_SUPPORT
31#define CONFIG_SPL_SERIAL_SUPPORT
32#define CONFIG_SPL_FLUSH_IMAGE
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LIBGENERIC_SUPPORT
35#define CONFIG_SPL_LIBCOMMON_SUPPORT
36#define CONFIG_SPL_I2C_SUPPORT
37#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38#define CONFIG_FSL_LAW /* Use common FSL init code */
39#define CONFIG_SYS_TEXT_BASE 0x00201000
40#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
41#define CONFIG_SPL_PAD_TO 0x40000
42#define CONFIG_SPL_MAX_SIZE 0x28000
43#define RESET_VECTOR_OFFSET 0x27FFC
44#define BOOT_PAGE_OFFSET 0x27000
45
46#ifdef CONFIG_NAND
47#define CONFIG_SPL_NAND_SUPPORT
48#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53#define CONFIG_SPL_NAND_BOOT
York Sun1cb19fb2013-06-27 10:48:29 -070054#endif
55
Shaohui Xieb6036992014-04-22 15:10:44 +080056#ifdef CONFIG_SDCARD
57#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58#define CONFIG_SPL_MMC_SUPPORT
59#define CONFIG_SPL_MMC_MINIMAL
60#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
61#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
62#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
63#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
64#ifndef CONFIG_SPL_BUILD
65#define CONFIG_SYS_MPC85XX_NO_RESETVEC
66#endif
67#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68#define CONFIG_SPL_MMC_BOOT
69#endif
70
71#ifdef CONFIG_SPL_BUILD
72#define CONFIG_SPL_SKIP_RELOCATE
73#define CONFIG_SPL_COMMON_INIT_DDR
74#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
75#define CONFIG_SYS_NO_FLASH
76#endif
77
78#endif
79#endif /* CONFIG_RAMBOOT_PBL */
80
York Sun1cb19fb2013-06-27 10:48:29 -070081#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
82/* Set 1M boot space */
83#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
84#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
85 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
86#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
87#define CONFIG_SYS_NO_FLASH
88#endif
89
90#define CONFIG_SRIO_PCIE_BOOT_MASTER
91#define CONFIG_DDR_ECC
92
York Sunee52b182012-10-11 07:13:37 +000093#include "t4qds.h"
York Sun1cb19fb2013-06-27 10:48:29 -070094
95#ifdef CONFIG_SYS_NO_FLASH
96#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
97#define CONFIG_ENV_IS_NOWHERE
98#endif
99#else
100#define CONFIG_FLASH_CFI_DRIVER
101#define CONFIG_SYS_FLASH_CFI
102#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
103#endif
104
105#if defined(CONFIG_SPIFLASH)
106#define CONFIG_SYS_EXTRA_ENV_RELOC
107#define CONFIG_ENV_IS_IN_SPI_FLASH
108#define CONFIG_ENV_SPI_BUS 0
109#define CONFIG_ENV_SPI_CS 0
110#define CONFIG_ENV_SPI_MAX_HZ 10000000
111#define CONFIG_ENV_SPI_MODE 0
112#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
113#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
114#define CONFIG_ENV_SECT_SIZE 0x10000
115#elif defined(CONFIG_SDCARD)
116#define CONFIG_SYS_EXTRA_ENV_RELOC
117#define CONFIG_ENV_IS_IN_MMC
118#define CONFIG_SYS_MMC_ENV_DEV 0
119#define CONFIG_ENV_SIZE 0x2000
Shaohui Xieb6036992014-04-22 15:10:44 +0800120#define CONFIG_ENV_OFFSET (512 * 0x800)
York Sun1cb19fb2013-06-27 10:48:29 -0700121#elif defined(CONFIG_NAND)
122#define CONFIG_SYS_EXTRA_ENV_RELOC
123#define CONFIG_ENV_IS_IN_NAND
Shaohui Xieb6036992014-04-22 15:10:44 +0800124#define CONFIG_ENV_SIZE 0x2000
125#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
York Sun1cb19fb2013-06-27 10:48:29 -0700126#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
127#define CONFIG_ENV_IS_IN_REMOTE
128#define CONFIG_ENV_ADDR 0xffe20000
129#define CONFIG_ENV_SIZE 0x2000
130#elif defined(CONFIG_ENV_IS_NOWHERE)
131#define CONFIG_ENV_SIZE 0x2000
132#else
133#define CONFIG_ENV_IS_IN_FLASH
134#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
135#define CONFIG_ENV_SIZE 0x2000
136#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
137#endif
138
139#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
140#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
141
142#ifndef __ASSEMBLY__
143unsigned long get_board_sys_clk(void);
144unsigned long get_board_ddr_clk(void);
145#endif
146
147/* EEPROM */
148#define CONFIG_ID_EEPROM
149#define CONFIG_SYS_I2C_EEPROM_NXID
150#define CONFIG_SYS_EEPROM_BUS_NUM 0
151#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
152#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
153
154/*
155 * DDR Setup
156 */
157#define CONFIG_SYS_SPD_BUS_NUM 0
158#define SPD_EEPROM_ADDRESS1 0x51
159#define SPD_EEPROM_ADDRESS2 0x52
160#define SPD_EEPROM_ADDRESS3 0x53
161#define SPD_EEPROM_ADDRESS4 0x54
162#define SPD_EEPROM_ADDRESS5 0x55
163#define SPD_EEPROM_ADDRESS6 0x56
164#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
165#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
166
167/*
168 * IFC Definitions
169 */
170#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
171#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
172 + 0x8000000) | \
173 CSPR_PORT_SIZE_16 | \
174 CSPR_MSEL_NOR | \
175 CSPR_V)
176#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
177#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
182/* NOR Flash Timing Params */
183#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
184
185#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186 FTIM0_NOR_TEADC(0x5) | \
187 FTIM0_NOR_TEAHC(0x5))
188#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189 FTIM1_NOR_TRAD_NOR(0x1A) |\
190 FTIM1_NOR_TSEQRAD_NOR(0x13))
191#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192 FTIM2_NOR_TCH(0x4) | \
193 FTIM2_NOR_TWPH(0x0E) | \
194 FTIM2_NOR_TWP(0x1c))
195#define CONFIG_SYS_NOR_FTIM3 0x0
196
197#define CONFIG_SYS_FLASH_QUIET_TEST
198#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
199
200#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
201#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
202#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204
205#define CONFIG_SYS_FLASH_EMPTY_INFO
206#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
207 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
208
209#define CONFIG_FSL_QIXIS /* use common QIXIS code */
210#define QIXIS_BASE 0xffdf0000
211#define QIXIS_LBMAP_SWITCH 6
212#define QIXIS_LBMAP_MASK 0x0f
213#define QIXIS_LBMAP_SHIFT 0
214#define QIXIS_LBMAP_DFLTBANK 0x00
215#define QIXIS_LBMAP_ALTBANK 0x04
216#define QIXIS_RST_CTL_RESET 0x83
York Sunc63e1372013-06-25 11:37:48 -0700217#define QIXIS_RST_FORCE_MEM 0x1
York Sun1cb19fb2013-06-27 10:48:29 -0700218#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
219#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
220#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800221#define QIXIS_BRDCFG5 0x55
222#define QIXIS_MUX_SDHC 2
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800223#define QIXIS_MUX_SDHC_WIDTH8 1
York Sun1cb19fb2013-06-27 10:48:29 -0700224#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
225
226#define CONFIG_SYS_CSPR3_EXT (0xf)
227#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
228 | CSPR_PORT_SIZE_8 \
229 | CSPR_MSEL_GPCM \
230 | CSPR_V)
231#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
232#define CONFIG_SYS_CSOR3 0x0
233/* QIXIS Timing parameters for IFC CS3 */
234#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
235 FTIM0_GPCM_TEADC(0x0e) | \
236 FTIM0_GPCM_TEAHC(0x0e))
237#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
238 FTIM1_GPCM_TRAD(0x3f))
239#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800240 FTIM2_GPCM_TCH(0x8) | \
York Sun1cb19fb2013-06-27 10:48:29 -0700241 FTIM2_GPCM_TWP(0x1f))
242#define CONFIG_SYS_CS3_FTIM3 0x0
243
244/* NAND Flash on IFC */
245#define CONFIG_NAND_FSL_IFC
246#define CONFIG_SYS_NAND_BASE 0xff800000
247#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
248
249#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
250#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
251 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
252 | CSPR_MSEL_NAND /* MSEL = NAND */ \
253 | CSPR_V)
254#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
255
256#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
257 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
258 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
259 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
260 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
261 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
262 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
263
264#define CONFIG_SYS_NAND_ONFI_DETECTION
265
266/* ONFI NAND Flash mode0 Timing Params */
267#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
268 FTIM0_NAND_TWP(0x18) | \
269 FTIM0_NAND_TWCHT(0x07) | \
270 FTIM0_NAND_TWH(0x0a))
271#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
272 FTIM1_NAND_TWBE(0x39) | \
273 FTIM1_NAND_TRR(0x0e) | \
274 FTIM1_NAND_TRP(0x18))
275#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
276 FTIM2_NAND_TREH(0x0a) | \
277 FTIM2_NAND_TWHRE(0x1e))
278#define CONFIG_SYS_NAND_FTIM3 0x0
279
280#define CONFIG_SYS_NAND_DDR_LAW 11
281
282#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
283#define CONFIG_SYS_MAX_NAND_DEVICE 1
York Sun1cb19fb2013-06-27 10:48:29 -0700284#define CONFIG_CMD_NAND
285
286#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530287#define CONFIG_SYS_NAND_MAX_OOBFREE 2
288#define CONFIG_SYS_NAND_MAX_ECCPOS 256
York Sun1cb19fb2013-06-27 10:48:29 -0700289
290#if defined(CONFIG_NAND)
291#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
292#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
293#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
294#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
295#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
296#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
297#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
298#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shaohui Xieb6036992014-04-22 15:10:44 +0800299#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
300#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
301#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
302#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
303#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
304#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
305#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
306#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
307#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
308#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
York Sun1cb19fb2013-06-27 10:48:29 -0700309#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
310#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
311#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
312#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
313#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
314#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
315#else
316#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
317#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
318#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
319#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
320#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
321#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
322#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
323#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shaohui Xieb6036992014-04-22 15:10:44 +0800324#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
325#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
326#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
327#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
328#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
329#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
330#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
331#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
York Sun1cb19fb2013-06-27 10:48:29 -0700332#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
333#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
334#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
335#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
336#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
337#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
338#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
339#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
340#endif
York Sun1cb19fb2013-06-27 10:48:29 -0700341
342#if defined(CONFIG_RAMBOOT_PBL)
343#define CONFIG_SYS_RAMBOOT
344#endif
345
York Sun1cb19fb2013-06-27 10:48:29 -0700346/* I2C */
347#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
348#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
349#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
350#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
351
352#define I2C_MUX_CH_DEFAULT 0x8
353#define I2C_MUX_CH_VOL_MONITOR 0xa
354#define I2C_MUX_CH_VSC3316_FS 0xc
355#define I2C_MUX_CH_VSC3316_BS 0xd
356
357/* Voltage monitor on channel 2*/
358#define I2C_VOL_MONITOR_ADDR 0x40
359#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
360#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
361#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
362
363/* VSC Crossbar switches */
364#define CONFIG_VSC_CROSSBAR
365#define VSC3316_FSM_TX_ADDR 0x70
366#define VSC3316_FSM_RX_ADDR 0x71
367
368/*
369 * RapidIO
370 */
371
372/*
373 * for slave u-boot IMAGE instored in master memory space,
374 * PHYS must be aligned based on the SIZE
375 */
Liu Gange4911812014-05-15 14:30:34 +0800376#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
377#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
378#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
379#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sun1cb19fb2013-06-27 10:48:29 -0700380/*
381 * for slave UCODE and ENV instored in master memory space,
382 * PHYS must be aligned based on the SIZE
383 */
Liu Gange4911812014-05-15 14:30:34 +0800384#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sun1cb19fb2013-06-27 10:48:29 -0700385#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
386#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
387
388/* slave core release by master*/
389#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
390#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
391
392/*
393 * SRIO_PCIE_BOOT - SLAVE
394 */
395#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
396#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
397#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
398 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
399#endif
400/*
401 * eSPI - Enhanced SPI
402 */
York Sun1cb19fb2013-06-27 10:48:29 -0700403#define CONFIG_SF_DEFAULT_SPEED 10000000
404#define CONFIG_SF_DEFAULT_MODE 0
405
York Sun1cb19fb2013-06-27 10:48:29 -0700406/* Qman/Bman */
407#ifndef CONFIG_NOBQFMAN
408#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
409#define CONFIG_SYS_BMAN_NUM_PORTALS 50
410#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
411#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
412#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500413#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
414#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
415#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
416#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
417#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
418 CONFIG_SYS_BMAN_CENA_SIZE)
419#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
420#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
York Sun1cb19fb2013-06-27 10:48:29 -0700421#define CONFIG_SYS_QMAN_NUM_PORTALS 50
422#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
423#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
424#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500425#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
426#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
427#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
428#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
429#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
430 CONFIG_SYS_QMAN_CENA_SIZE)
431#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
432#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
York Sun1cb19fb2013-06-27 10:48:29 -0700433
434#define CONFIG_SYS_DPAA_FMAN
435#define CONFIG_SYS_DPAA_PME
436#define CONFIG_SYS_PMAN
437#define CONFIG_SYS_DPAA_DCE
Minghuan Lian0795eff2013-07-03 18:32:41 +0800438#define CONFIG_SYS_DPAA_RMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700439#define CONFIG_SYS_INTERLAKEN
440
441/* Default address of microcode for the Linux Fman driver */
442#if defined(CONFIG_SPIFLASH)
443/*
444 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
445 * env, so we got 0x110000.
446 */
447#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800448#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sun1cb19fb2013-06-27 10:48:29 -0700449#elif defined(CONFIG_SDCARD)
450/*
451 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shaohui Xieb6036992014-04-22 15:10:44 +0800452 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
453 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
York Sun1cb19fb2013-06-27 10:48:29 -0700454 */
455#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shaohui Xieb6036992014-04-22 15:10:44 +0800456#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
York Sun1cb19fb2013-06-27 10:48:29 -0700457#elif defined(CONFIG_NAND)
458#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shaohui Xieb6036992014-04-22 15:10:44 +0800459#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
York Sun1cb19fb2013-06-27 10:48:29 -0700460#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
461/*
462 * Slave has no ucode locally, it can fetch this from remote. When implementing
463 * in two corenet boards, slave's ucode could be stored in master's memory
464 * space, the address can be mapped from slave TLB->slave LAW->
465 * slave SRIO or PCIE outbound window->master inbound window->
466 * master LAW->the ucode address in master's memory space.
467 */
468#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800469#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sun1cb19fb2013-06-27 10:48:29 -0700470#else
471#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800472#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sun1cb19fb2013-06-27 10:48:29 -0700473#endif
474#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
475#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
476#endif /* CONFIG_NOBQFMAN */
477
478#ifdef CONFIG_SYS_DPAA_FMAN
479#define CONFIG_FMAN_ENET
480#define CONFIG_PHYLIB_10G
481#define CONFIG_PHY_VITESSE
482#define CONFIG_PHY_TERANETICS
483#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
484#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
485#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
486#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
487#define FM1_10GEC1_PHY_ADDR 0x0
488#define FM1_10GEC2_PHY_ADDR 0x1
489#define FM2_10GEC1_PHY_ADDR 0x2
490#define FM2_10GEC2_PHY_ADDR 0x3
491#endif
492
York Sun1cb19fb2013-06-27 10:48:29 -0700493/* SATA */
494#ifdef CONFIG_FSL_SATA_V2
495#define CONFIG_LIBATA
496#define CONFIG_FSL_SATA
497
498#define CONFIG_SYS_SATA_MAX_DEVICE 2
499#define CONFIG_SATA1
500#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
501#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
502#define CONFIG_SATA2
503#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
504#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
505
506#define CONFIG_LBA48
507#define CONFIG_CMD_SATA
508#define CONFIG_DOS_PARTITION
York Sun1cb19fb2013-06-27 10:48:29 -0700509#endif
510
511#ifdef CONFIG_FMAN_ENET
512#define CONFIG_MII /* MII PHY management */
513#define CONFIG_ETHPRIME "FM1@DTSEC1"
514#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
515#endif
516
Ruchika Gupta737537e2014-10-15 11:35:31 +0530517/* Hash command with SHA acceleration supported in hardware */
518#ifdef CONFIG_FSL_CAAM
519#define CONFIG_CMD_HASH
520#define CONFIG_SHA_HW_ACCEL
521#endif
522
York Sun1cb19fb2013-06-27 10:48:29 -0700523/*
524* USB
525*/
York Sun1cb19fb2013-06-27 10:48:29 -0700526#define CONFIG_USB_STORAGE
527#define CONFIG_USB_EHCI
528#define CONFIG_USB_EHCI_FSL
529#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
York Sun1cb19fb2013-06-27 10:48:29 -0700530#define CONFIG_HAS_FSL_DR_USB
531
532#define CONFIG_MMC
533
534#ifdef CONFIG_MMC
535#define CONFIG_FSL_ESDHC
536#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
537#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
York Sun1cb19fb2013-06-27 10:48:29 -0700538#define CONFIG_GENERIC_MMC
York Sun1cb19fb2013-06-27 10:48:29 -0700539#define CONFIG_DOS_PARTITION
Haijun.Zhangef38f3f2013-10-31 09:38:19 +0800540#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800541#define CONFIG_ESDHC_DETECT_QUIRK \
542 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
543 IS_SVR_REV(get_svr(), 1, 0))
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800544#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
545 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
York Sun1cb19fb2013-06-27 10:48:29 -0700546#endif
547
548#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
549
550#define __USB_PHY_TYPE utmi
551
552/*
553 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
554 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
555 * interleaving. It can be cacheline, page, bank, superbank.
556 * See doc/README.fsl-ddr for details.
557 */
558#ifdef CONFIG_PPC_T4240
559#define CTRL_INTLV_PREFERED 3way_4KB
560#else
561#define CTRL_INTLV_PREFERED cacheline
562#endif
563
564#define CONFIG_EXTRA_ENV_SETTINGS \
565 "hwconfig=fsl_ddr:" \
566 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
567 "bank_intlv=auto;" \
568 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
569 "netdev=eth0\0" \
570 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
571 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
572 "tftpflash=tftpboot $loadaddr $uboot && " \
573 "protect off $ubootaddr +$filesize && " \
574 "erase $ubootaddr +$filesize && " \
575 "cp.b $loadaddr $ubootaddr $filesize && " \
576 "protect on $ubootaddr +$filesize && " \
577 "cmp.b $loadaddr $ubootaddr $filesize\0" \
578 "consoledev=ttyS0\0" \
579 "ramdiskaddr=2000000\0" \
580 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
581 "fdtaddr=c00000\0" \
582 "fdtfile=t4240qds/t4240qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500583 "bdev=sda3\0"
York Sun1cb19fb2013-06-27 10:48:29 -0700584
585#define CONFIG_HVBOOT \
586 "setenv bootargs config-addr=0x60000000; " \
587 "bootm 0x01000000 - 0x00f00000"
588
589#define CONFIG_ALU \
590 "setenv bootargs root=/dev/$bdev rw " \
591 "console=$consoledev,$baudrate $othbootargs;" \
592 "cpu 1 release 0x01000000 - - -;" \
593 "cpu 2 release 0x01000000 - - -;" \
594 "cpu 3 release 0x01000000 - - -;" \
595 "cpu 4 release 0x01000000 - - -;" \
596 "cpu 5 release 0x01000000 - - -;" \
597 "cpu 6 release 0x01000000 - - -;" \
598 "cpu 7 release 0x01000000 - - -;" \
599 "go 0x01000000"
600
601#define CONFIG_LINUX \
602 "setenv bootargs root=/dev/ram rw " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "setenv ramdiskaddr 0x02000000;" \
605 "setenv fdtaddr 0x00c00000;" \
606 "setenv loadaddr 0x1000000;" \
607 "bootm $loadaddr $ramdiskaddr $fdtaddr"
608
609#define CONFIG_HDBOOT \
610 "setenv bootargs root=/dev/$bdev rw " \
611 "console=$consoledev,$baudrate $othbootargs;" \
612 "tftp $loadaddr $bootfile;" \
613 "tftp $fdtaddr $fdtfile;" \
614 "bootm $loadaddr - $fdtaddr"
615
616#define CONFIG_NFSBOOTCOMMAND \
617 "setenv bootargs root=/dev/nfs rw " \
618 "nfsroot=$serverip:$rootpath " \
619 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
620 "console=$consoledev,$baudrate $othbootargs;" \
621 "tftp $loadaddr $bootfile;" \
622 "tftp $fdtaddr $fdtfile;" \
623 "bootm $loadaddr - $fdtaddr"
624
625#define CONFIG_RAMBOOTCOMMAND \
626 "setenv bootargs root=/dev/ram rw " \
627 "console=$consoledev,$baudrate $othbootargs;" \
628 "tftp $ramdiskaddr $ramdiskfile;" \
629 "tftp $loadaddr $bootfile;" \
630 "tftp $fdtaddr $fdtfile;" \
631 "bootm $loadaddr $ramdiskaddr $fdtaddr"
632
633#define CONFIG_BOOTCOMMAND CONFIG_LINUX
634
York Sun1cb19fb2013-06-27 10:48:29 -0700635#include <asm/fsl_secure_boot.h>
York Sun1cb19fb2013-06-27 10:48:29 -0700636
637#endif /* __CONFIG_H */