blob: 30518544dd65827e723d054785b1edcc8a3c0017 [file] [log] [blame]
Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Timur Tabi9ff32d82010-03-29 12:51:07 -05002 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
Jon Loeligercb5965f2006-05-31 12:44:44 -05003 * Jeff Brown
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05007 */
8
9#include <common.h>
10#include <watchdog.h>
11#include <command.h>
12#include <asm/cache.h>
Becky Brucee34a0e92008-05-08 19:02:51 -050013#include <asm/mmu.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050014#include <mpc86xx.h>
Becky Bruce4f93f8b2008-01-23 16:31:06 -060015#include <asm/fsl_law.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050016
Poonam Aggrwal0e870982009-07-31 12:08:14 +053017DECLARE_GLOBAL_DATA_PTR;
18
Peter Tyser4ef630d2009-02-05 11:25:25 -060019/*
20 * Default board reset function
21 */
22static void
23__board_reset(void)
24{
25 /* Do nothing */
26}
Peter Tyserf9a109b2009-04-20 11:08:46 -050027void board_reset(void) __attribute__((weak, alias("__board_reset")));
Peter Tyser4ef630d2009-02-05 11:25:25 -060028
29
Jon Loeligerffff3ae2006-08-22 12:06:18 -050030int
31checkcpu(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050032{
33 sys_info_t sysinfo;
34 uint pvr, svr;
Jon Loeligerdebb7352006-04-26 17:58:56 -050035 uint major, minor;
Peter Tysera1c8a712009-02-06 14:30:40 -060036 char buf1[32], buf2[32];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Jon Loeliger9553df82007-10-16 15:26:51 -050038 volatile ccsr_gur_t *gur = &immap->im_gur;
Kumar Gala480f6172009-06-18 08:23:01 -050039 struct cpu_type *cpu;
Peter Tysera1c8a712009-02-06 14:30:40 -060040 uint msscr0 = mfspr(MSSCR0);
Jon Loeligerdebb7352006-04-26 17:58:56 -050041
42 svr = get_svr();
Jon Loeligerdebb7352006-04-26 17:58:56 -050043 major = SVR_MAJ(svr);
44 minor = SVR_MIN(svr);
45
Poonam Aggrwal21170c82009-09-03 19:42:40 +053046 if (cpu_numcores() > 1) {
47#ifndef CONFIG_MP
48 puts("Unicore software on multiprocessor system!!\n"
49 "To enable mutlticore build define CONFIG_MP\n");
50#endif
51 }
Peter Tysera1c8a712009-02-06 14:30:40 -060052 puts("CPU: ");
53
Simon Glass67ac13b2012-12-13 20:48:48 +000054 cpu = gd->arch.cpu;
Poonam Aggrwal0e870982009-07-31 12:08:14 +053055
Poonam Aggrwal58442dc2009-09-02 13:35:21 +053056 puts(cpu->name);
Kumar Gala480f6172009-06-18 08:23:01 -050057
Jon Loeligerdebb7352006-04-26 17:58:56 -050058 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
Peter Tysera1c8a712009-02-06 14:30:40 -060059 puts("Core: ");
60
61 pvr = get_pvr();
Peter Tysera1c8a712009-02-06 14:30:40 -060062 major = PVR_E600_MAJ(pvr);
63 minor = PVR_E600_MIN(pvr);
64
Fabio Estevam6770c5e2013-04-21 13:11:02 -030065 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
Peter Tysera1c8a712009-02-06 14:30:40 -060066 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
67 puts("\n Core1Translation Enabled");
68 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
69
70 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
Jon Loeligerdebb7352006-04-26 17:58:56 -050071
72 get_sys_info(&sysinfo);
73
Peter Tysera1c8a712009-02-06 14:30:40 -060074 puts("Clock Configuration:\n");
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053075 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
76 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
Peter Tysera1c8a712009-02-06 14:30:40 -060077 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053078 strmhz(buf1, sysinfo.freq_systembus / 2),
79 strmhz(buf2, sysinfo.freq_systembus));
Jon Loeliger5c9efb32006-04-27 10:15:16 -050080
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053081 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
82 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Jon Loeligerdebb7352006-04-26 17:58:56 -050083 } else {
Wolfgang Denka9f3acb2009-01-12 14:50:35 +010084 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053085 sysinfo.freq_localbus);
Jon Loeligerdebb7352006-04-26 17:58:56 -050086 }
87
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -050088 puts("L1: D-cache 32 KiB enabled\n");
89 puts(" I-cache 32 KiB enabled\n");
Peter Tysera1c8a712009-02-06 14:30:40 -060090
91 puts("L2: ");
92 if (get_l2cr() & 0x80000000) {
93#if defined(CONFIG_MPC8610)
94 puts("256");
95#elif defined(CONFIG_MPC8641)
96 puts("512");
97#endif
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -050098 puts(" KiB enabled\n");
Peter Tysera1c8a712009-02-06 14:30:40 -060099 } else {
Jon Loeligercb5965f2006-05-31 12:44:44 -0500100 puts("Disabled\n");
Peter Tysera1c8a712009-02-06 14:30:40 -0600101 }
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500102
103 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500104}
105
106
Peter Tyserc22a7112010-12-03 10:28:47 -0600107int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Jon Loeligerdebb7352006-04-26 17:58:56 -0500108{
Peter Tyser4ef630d2009-02-05 11:25:25 -0600109 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
110 volatile ccsr_gur_t *gur = &immap->im_gur;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500111
Peter Tyser4ef630d2009-02-05 11:25:25 -0600112 /* Attempt board-specific reset */
113 board_reset();
Jon Loeligerdebb7352006-04-26 17:58:56 -0500114
Peter Tyser4ef630d2009-02-05 11:25:25 -0600115 /* Next try asserting HRESET_REQ */
116 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500117
Peter Tyser4ef630d2009-02-05 11:25:25 -0600118 while (1)
119 ;
Peter Tyserc22a7112010-12-03 10:28:47 -0600120
121 return 1;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500122}
123
124
Jon Loeligerdebb7352006-04-26 17:58:56 -0500125/*
126 * Get timebase clock frequency
127 */
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500128unsigned long
129get_tbclk(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500130{
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500131 sys_info_t sys_info;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500132
133 get_sys_info(&sys_info);
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530134 return (sys_info.freq_systembus + 3L) / 4L;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500135}
136
Jon Loeligerdebb7352006-04-26 17:58:56 -0500137
138#if defined(CONFIG_WATCHDOG)
139void
140watchdog_reset(void)
141{
Jason Jin3473ab72008-05-13 11:50:36 +0800142#if defined(CONFIG_MPC8610)
143 /*
144 * This actually feed the hard enabled watchdog.
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jason Jin3473ab72008-05-13 11:50:36 +0800147 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
148 volatile ccsr_gur_t *gur = &immap->im_gur;
149 u32 tmp = gur->pordevsr;
150
151 if (tmp & 0x4000) {
152 wdt->swsrr = 0x556c;
153 wdt->swsrr = 0xaa39;
154 }
155#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500156}
157#endif /* CONFIG_WATCHDOG */
158
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600159/*
160 * Print out the state of various machine registers.
Becky Brucee34a0e92008-05-08 19:02:51 -0500161 * Currently prints out LAWs, BR0/OR0, and BATs
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600162 */
163void mpc86xx_reginfo(void)
164{
Becky Brucee34a0e92008-05-08 19:02:51 -0500165 print_bats();
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600166 print_laws();
Becky Brucef51cdaf2010-06-17 11:37:20 -0500167 print_lbc_regs();
Jon Loeligerdebb7352006-04-26 17:58:56 -0500168}
Timur Tabi9ff32d82010-03-29 12:51:07 -0500169
170/*
171 * Set the DDR BATs to reflect the actual size of DDR.
172 *
173 * dram_size is the actual size of DDR, in bytes
174 *
175 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
176 * are using a single BAT to cover DDR.
177 *
178 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
179 * is not defined) then we might have a situation where U-Boot will attempt
180 * to relocated itself outside of the region mapped by DBAT0.
181 * This will cause a machine check.
182 *
183 * Currently we are limited to power of two sized DDR since we only use a
184 * single bat. If a non-power of two size is used that is less than
185 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
186 *
187 */
188void setup_ddr_bat(phys_addr_t dram_size)
189{
190 unsigned long batu, bl;
191
192 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
193
194 if (BATU_SIZE(bl) != dram_size) {
195 u64 sz = (u64)dram_size - BATU_SIZE(bl);
196 print_size(sz, " left unmapped\n");
197 }
198
199 batu = bl | BATU_VS | BATU_VP;
200 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
201 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
202}