blob: 59585af83a696b4a95e198ae42c8714aa2928733 [file] [log] [blame]
wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +000011 */
12
13/*
14 * CPU specific code
15 */
16
17#include <common.h>
18#include <command.h>
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020019#include <asm/system.h>
Albert ARIBAUDcd6cc342014-04-15 16:13:48 +020020#include <asm/io.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000021
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020022static void cache_flush(void);
23
wdenk4a9cbbe2002-08-27 09:48:53 +000024int cleanup_before_linux (void)
25{
26 /*
27 * this function is called just before we call linux
28 * it prepares the processor for linux
29 *
30 * just disable everything that can disturb booting linux
31 */
32
wdenk4a9cbbe2002-08-27 09:48:53 +000033 disable_interrupts ();
34
35 /* turn off I-cache */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020036 icache_disable();
37 dcache_disable();
wdenk4a9cbbe2002-08-27 09:48:53 +000038
39 /* flush I-cache */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020040 cache_flush();
wdenk4a9cbbe2002-08-27 09:48:53 +000041
42 return (0);
43}
44
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020045/* flush I/D-cache */
46static void cache_flush (void)
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020047{
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020048 unsigned long i = 0;
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020049
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020050 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
wdenk4a9cbbe2002-08-27 09:48:53 +000051}
Albert ARIBAUDcd6cc342014-04-15 16:13:48 +020052
53#define RST_BASE 0x90030000
54#define RSRR 0x00
55#define RCSR 0x04
56
57__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
58{
59 /* repeat endlessly */
60 while (1) {
61 writel(0, RST_BASE + RCSR);
62 writel(1, RST_BASE + RSRR);
63 }
64}