blob: c809a6b363f4718a45d428ed7278da27818fddd9 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2001
6 * James F. Dougherty (jfd@cs.stanford.edu)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 *
29 * Configuration settings for the MOUSSE board.
30 * See also: http://www.vooha.com/
31 *
32 */
33
34/* ------------------------------------------------------------------------- */
35
36/*
37 * board/config.h - configuration options, board specific
38 */
39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43/*
44 * High Level Configuration Options
45 * (easy to change)
46 */
47
48#define CONFIG_MPC824X 1
49#define CONFIG_MPC8240 1
50#define CONFIG_MOUSSE 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020051
52#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010053#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_ADDR_MAP_B 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056
wdenkfe8c2802002-11-03 00:38:21 +000057#define CONFIG_CONS_INDEX 1
58#define CONFIG_BAUDRATE 9600
59#if 1
60#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
61#else
62#define CONFIG_BOOTCOMMAND "bootm ffe10000"
63#endif
64#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
65#define CONFIG_BOOTDELAY 3
Jon Loeliger8353e132007-07-08 14:14:17 -050066
67
68/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050069 * BOOTP options
70 */
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
77/*
Jon Loeliger8353e132007-07-08 14:14:17 -050078 * Command line configuration.
79 */
80#include <config_cmd_default.h>
81
82#define CONFIG_CMD_ASKENV
83#define CONFIG_CMD_DATE
84
85
wdenkfe8c2802002-11-03 00:38:21 +000086#define CONFIG_ENV_OVERWRITE 1
87#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
88
89#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
Jon Loeliger8353e132007-07-08 14:14:17 -050090
wdenkfe8c2802002-11-03 00:38:21 +000091#include "../board/mousse/mousse.h"
92
93/*
94 * Miscellaneous configurable options
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_LONGHELP /* undef to save memory */
97#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
98#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
99#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
100#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
103#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkfe8c2802002-11-03 00:38:21 +0000104
105/*-----------------------------------------------------------------------
106 * Start addresses for the final memory configuration
107 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkfe8c2802002-11-03 00:38:21 +0000109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkfe8c2802002-11-03 00:38:21 +0000111
112#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000114#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000116#endif
117
118#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */
wdenkfe8c2802002-11-03 00:38:21 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
wdenkfe8c2802002-11-03 00:38:21 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
126#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenkfe8c2802002-11-03 00:38:21 +0000127
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkfe8c2802002-11-03 00:38:21 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_ISA_MEM 0xFD000000
132#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkfe8c2802002-11-03 00:38:21 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_FLASH_BASE 0xFFF00000
135#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024))
136#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkfe8c2802002-11-03 00:38:21 +0000137#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
138#define FLASH_BASE0_SIZE 0x80000 /* 512K */
139#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
140 1MB - 64K FLASH0 SEG =960K
141 (size=0xf0000)*/
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000144
145/*
146 * NS16550 Configuration
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_NS16550
149#define CONFIG_SYS_NS16550_SERIAL
wdenkfe8c2802002-11-03 00:38:21 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkfe8c2802002-11-03 00:38:21 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_NS16550_CLK 18432000
wdenkfe8c2802002-11-03 00:38:21 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_NS16550_COM1 0xFFE08080
wdenkfe8c2802002-11-03 00:38:21 +0000156
157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
Wolfgang Denk553f0982010-10-26 13:32:32 +0200161#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000164
165/*
166 * Low Level Configuration Settings
167 * (address mappings, register initial values, etc.)
168 * You should know what you are doing if you make changes here.
169 * For the detail description refer to the MPC8240 user's manual.
170 */
171
172#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
173#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_HZ 1000
wdenkfe8c2802002-11-03 00:38:21 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_ETH_DEV_FN 0x00
177#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkfe8c2802002-11-03 00:38:21 +0000178
179
180 /* Bit-field values for MCCR1.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_ROMNAL 8
183#define CONFIG_SYS_ROMFAL 8
wdenkfe8c2802002-11-03 00:38:21 +0000184
185 /* Bit-field values for MCCR2.
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */
wdenkfe8c2802002-11-03 00:38:21 +0000188
189 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BSTOPRE 0x79
wdenkfe8c2802002-11-03 00:38:21 +0000192
193#ifdef INCLUDE_ECC
194#define USE_ECC 1
195#else /* INCLUDE_ECC */
196#define USE_ECC 0
197#endif /* INCLUDE_ECC */
198
199
200 /* Bit-field values for MCCR3.
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
203#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */
wdenkfe8c2802002-11-03 00:38:21 +0000204
205 /* Bit-field values for MCCR4.
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
208#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
209#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
210#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
211#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
212#define CONFIG_SYS_ACTORW 2
213#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
wdenkfe8c2802002-11-03 00:38:21 +0000214
215/* Memory bank settings.
216 * Only bits 20-29 are actually used from these vales to set the
217 * start/end addresses. The upper two bits will always be 0, and the lower
218 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
219 * address. Refer to the MPC8240 book.
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */
wdenkfe8c2802002-11-03 00:38:21 +0000222
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_BANK0_START 0x00000000
225#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1)
226#define CONFIG_SYS_BANK0_ENABLE 1
227#define CONFIG_SYS_BANK1_START 0x3ff00000
228#define CONFIG_SYS_BANK1_END 0x3fffffff
229#define CONFIG_SYS_BANK1_ENABLE 0
230#define CONFIG_SYS_BANK2_START 0x3ff00000
231#define CONFIG_SYS_BANK2_END 0x3fffffff
232#define CONFIG_SYS_BANK2_ENABLE 0
233#define CONFIG_SYS_BANK3_START 0x3ff00000
234#define CONFIG_SYS_BANK3_END 0x3fffffff
235#define CONFIG_SYS_BANK3_ENABLE 0
236#define CONFIG_SYS_BANK4_START 0x3ff00000
237#define CONFIG_SYS_BANK4_END 0x3fffffff
238#define CONFIG_SYS_BANK4_ENABLE 0
239#define CONFIG_SYS_BANK5_START 0x3ff00000
240#define CONFIG_SYS_BANK5_END 0x3fffffff
241#define CONFIG_SYS_BANK5_ENABLE 0
242#define CONFIG_SYS_BANK6_START 0x3ff00000
243#define CONFIG_SYS_BANK6_END 0x3fffffff
244#define CONFIG_SYS_BANK6_ENABLE 0
245#define CONFIG_SYS_BANK7_START 0x3ff00000
246#define CONFIG_SYS_BANK7_END 0x3fffffff
247#define CONFIG_SYS_BANK7_ENABLE 0
wdenkfe8c2802002-11-03 00:38:21 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_ODCR 0x7f
wdenkfe8c2802002-11-03 00:38:21 +0000250
251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
wdenk8bde7f72003-06-27 21:31:46 +0000253 see 8240 book for details*/
wdenkfe8c2802002-11-03 00:38:21 +0000254#define PCI_MEM_SPACE1_START 0x80000000
255#define PCI_MEM_SPACE2_START 0xfd000000
256
257/* IBAT/DBAT Configuration */
258/* Ram: 64MB, starts at address-0, r/w instruction/data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
260#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
261#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
262#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
wdenkfe8c2802002-11-03 00:38:21 +0000263
264/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
wdenkfe8c2802002-11-03 00:38:21 +0000266#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
wdenkfe8c2802002-11-03 00:38:21 +0000268 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
wdenkfe8c2802002-11-03 00:38:21 +0000271#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
273#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
wdenkfe8c2802002-11-03 00:38:21 +0000274
275/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
277#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
278#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
279#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
wdenkfe8c2802002-11-03 00:38:21 +0000280
281/* PCI Memory region 2: PCI Devices in 0xFD space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
283#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
284#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
285#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
wdenkfe8c2802002-11-03 00:38:21 +0000286
287
288/*
289 * For booting Linux, the board info and command line data
290 * have to be in the first 8 MB of memory, since this is
291 * the maximum mapped by the Linux kernel during initialization.
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000294
295/*-----------------------------------------------------------------------
296 * FLASH organization
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */
299#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
wdenkfe8c2802002-11-03 00:38:21 +0000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
302#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000303
304#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200305#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200306#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
307#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
wdenkfe8c2802002-11-03 00:38:21 +0000308#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200309#define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200310#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
311#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
312#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
wdenkfe8c2802002-11-03 00:38:21 +0000313#endif
314/*-----------------------------------------------------------------------
315 * Cache Configuration
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkfe8c2802002-11-03 00:38:21 +0000318
wdenkfe8c2802002-11-03 00:38:21 +0000319/* Localizations */
320#if 0
321#define CONFIG_ETHADDR 0:0:0:0:1:d
322#define CONFIG_IPADDR 172.16.40.113
323#define CONFIG_SERVERIP 172.16.40.111
324#else
325#define CONFIG_ETHADDR 0:0:0:0:1:d
326#define CONFIG_IPADDR 209.128.93.138
327#define CONFIG_SERVERIP 209.128.93.133
328#endif
329
330/*-----------------------------------------------------------------------
331 * PCI stuff
332 *-----------------------------------------------------------------------
333 */
334#define CONFIG_PCI /* include pci support */
335#undef CONFIG_PCI_PNP
336
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200337#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenkfe8c2802002-11-03 00:38:21 +0000338
339#define CONFIG_TULIP
340
341#endif /* __CONFIG_H */