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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Simple serial driver for Cogent motherboard serial ports
3 * for use during boot
4 */
5
6#include <common.h>
7#include <board/cogent/serial.h>
8
Wolfgang Denkd87080b2006-03-31 18:32:53 +02009DECLARE_GLOBAL_DATA_PTR;
10
wdenkc6097192002-11-03 00:24:07 +000011#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
12
13#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
14 (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
15
16#if CONFIG_CONS_INDEX == 1
17#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE
18#elif CONFIG_CONS_INDEX == 2
19#define CMA_MB_SERIAL_BASE CMA_MB_SERIALB_BASE
20#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
21#define CMA_MB_SERIAL_BASE CMA_MB_SER2A_BASE
22#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
23#define CMA_MB_SERIAL_BASE CMA_MB_SER2B_BASE
24#else
25#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
26#endif
27
28int serial_init (void)
29{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020030 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
wdenkc6097192002-11-03 00:24:07 +000031
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032 cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */
33 serial_setbrg ();
34 cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
35 cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */
36 cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
wdenkc6097192002-11-03 00:24:07 +000037
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038 return (0);
wdenkc6097192002-11-03 00:24:07 +000039}
40
Wolfgang Denkd87080b2006-03-31 18:32:53 +020041void serial_setbrg (void)
wdenkc6097192002-11-03 00:24:07 +000042{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020043 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
44 unsigned int divisor;
45 unsigned char lcr;
wdenkc6097192002-11-03 00:24:07 +000046
Wolfgang Denkd87080b2006-03-31 18:32:53 +020047 if ((divisor = br_to_div (gd->baudrate)) == 0)
48 divisor = DEFDIV;
wdenkc6097192002-11-03 00:24:07 +000049
Wolfgang Denkd87080b2006-03-31 18:32:53 +020050 lcr = cma_mb_reg_read (&mbsp->ser_lcr);
51 cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80); /* Access baud rate(set DLAB) */
52 cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
53 cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
54 cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */
wdenkc6097192002-11-03 00:24:07 +000055}
56
Wolfgang Denkd87080b2006-03-31 18:32:53 +020057void serial_putc (const char c)
wdenkc6097192002-11-03 00:24:07 +000058{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020059 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
wdenkc6097192002-11-03 00:24:07 +000060
Wolfgang Denkd87080b2006-03-31 18:32:53 +020061 if (c == '\n')
62 serial_putc ('\r');
wdenkc6097192002-11-03 00:24:07 +000063
Wolfgang Denkd87080b2006-03-31 18:32:53 +020064 while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
wdenkc6097192002-11-03 00:24:07 +000065
Wolfgang Denkd87080b2006-03-31 18:32:53 +020066 cma_mb_reg_write (&mbsp->ser_thr, c);
wdenkc6097192002-11-03 00:24:07 +000067}
68
Wolfgang Denkd87080b2006-03-31 18:32:53 +020069void serial_puts (const char *s)
wdenkc6097192002-11-03 00:24:07 +000070{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020071 while (*s != '\0')
72 serial_putc (*s++);
wdenkc6097192002-11-03 00:24:07 +000073}
74
Wolfgang Denkd87080b2006-03-31 18:32:53 +020075int serial_getc (void)
wdenkc6097192002-11-03 00:24:07 +000076{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020077 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
wdenkc6097192002-11-03 00:24:07 +000078
Wolfgang Denkd87080b2006-03-31 18:32:53 +020079 while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
wdenkc6097192002-11-03 00:24:07 +000080
Wolfgang Denkd87080b2006-03-31 18:32:53 +020081 return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
wdenkc6097192002-11-03 00:24:07 +000082}
83
Wolfgang Denkd87080b2006-03-31 18:32:53 +020084int serial_tstc (void)
wdenkc6097192002-11-03 00:24:07 +000085{
Wolfgang Denkd87080b2006-03-31 18:32:53 +020086 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
wdenkc6097192002-11-03 00:24:07 +000087
Wolfgang Denkd87080b2006-03-31 18:32:53 +020088 return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
wdenkc6097192002-11-03 00:24:07 +000089}
90
91#endif /* CONS_NONE */
92
93#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \
94 defined(CONFIG_KGDB_NONE)
95
96#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
97#error Console and kgdb are on the same serial port - this is not supported
98#endif
99
100#if CONFIG_KGDB_INDEX == 1
101#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE
102#elif CONFIG_KGDB_INDEX == 2
103#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALB_BASE
104#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
105#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2A_BASE
106#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
107#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2B_BASE
108#else
109#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
110#endif
111
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200112void kgdb_serial_init (void)
wdenkc6097192002-11-03 00:24:07 +0000113{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200114 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
115 unsigned int divisor;
wdenkc6097192002-11-03 00:24:07 +0000116
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200117 if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
118 divisor = DEFDIV;
wdenkc6097192002-11-03 00:24:07 +0000119
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200120 cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */
121 cma_mb_reg_write (&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB) */
122 cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
123 cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
124 cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
125 cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */
126 cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
wdenkc6097192002-11-03 00:24:07 +0000127
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200128 printf ("[on cma10x serial port B] ");
wdenkc6097192002-11-03 00:24:07 +0000129}
130
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200131void putDebugChar (int c)
wdenkc6097192002-11-03 00:24:07 +0000132{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200133 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
wdenkc6097192002-11-03 00:24:07 +0000134
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200135 while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
wdenkc6097192002-11-03 00:24:07 +0000136
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200137 cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
wdenkc6097192002-11-03 00:24:07 +0000138}
139
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200140void putDebugStr (const char *str)
wdenkc6097192002-11-03 00:24:07 +0000141{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200142 while (*str != '\0') {
143 if (*str == '\n')
144 putDebugChar ('\r');
145 putDebugChar (*str++);
146 }
wdenkc6097192002-11-03 00:24:07 +0000147}
148
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200149int getDebugChar (void)
wdenkc6097192002-11-03 00:24:07 +0000150{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200151 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
wdenkc6097192002-11-03 00:24:07 +0000152
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200153 while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
wdenkc6097192002-11-03 00:24:07 +0000154
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200155 return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
wdenkc6097192002-11-03 00:24:07 +0000156}
157
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200158void kgdb_interruptible (int yes)
wdenkc6097192002-11-03 00:24:07 +0000159{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200160 cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
wdenkc6097192002-11-03 00:24:07 +0000161
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200162 if (yes == 1) {
163 printf ("kgdb: turning serial ints on\n");
164 cma_mb_reg_write (&mbsp->ser_ier, 0xf);
165 } else {
166 printf ("kgdb: turning serial ints off\n");
167 cma_mb_reg_write (&mbsp->ser_ier, 0x0);
168 }
wdenkc6097192002-11-03 00:24:07 +0000169}
170
171#endif /* KGDB && KGDB_NONE */
172
173#endif /* CAPS & SERPAR */