blob: 26a626b4cbd59eea4eef55886213bf6c3d2cde66 [file] [log] [blame]
Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
Mike Frysinger395bce42008-02-24 23:58:13 -05002 * Driver for Blackfin On-Chip MAC device
Aubrey Li26bf7de2007-03-19 01:24:52 +08003 *
Mike Frysinger395bce42008-02-24 23:58:13 -05004 * Copyright (c) 2005-2008 Analog Device, Inc.
Aubrey Li26bf7de2007-03-19 01:24:52 +08005 *
Mike Frysinger395bce42008-02-24 23:58:13 -05006 * Licensed under the GPL-2 or later.
Aubrey Li26bf7de2007-03-19 01:24:52 +08007 */
8
9#include <common.h>
10#include <config.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +080011#include <net.h>
Ben Warren89973f82008-08-31 22:22:04 -070012#include <netdev.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +080013#include <command.h>
14#include <malloc.h>
Mike Frysingerac45af42008-10-14 04:52:00 -040015#include <miiphy.h>
Joe Hershberger875e0bc2016-08-08 11:28:40 -050016#include <linux/mdio.h>
Mike Frysingerac45af42008-10-14 04:52:00 -040017#include <linux/mii.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +080018
Mike Frysinger395bce42008-02-24 23:58:13 -050019#include <asm/blackfin.h>
Tom Rini130fbeb2014-02-20 10:14:10 -050020#include <asm/clock.h>
Mike Frysinger8339ad72010-06-02 05:56:22 -040021#include <asm/portmux.h>
Mike Frysingerd4d77302008-02-04 19:26:55 -050022#include <asm/mach-common/bits/dma.h>
23#include <asm/mach-common/bits/emac.h>
24#include <asm/mach-common/bits/pll.h>
25
Mike Frysinger395bce42008-02-24 23:58:13 -050026#include "bfin_mac.h"
27
Mike Frysingera7ec6ac2008-10-20 13:59:51 -040028#ifndef CONFIG_PHY_ADDR
29# define CONFIG_PHY_ADDR 1
30#endif
31#ifndef CONFIG_PHY_CLOCK_FREQ
32# define CONFIG_PHY_CLOCK_FREQ 2500000
33#endif
34
Aubrey Li26bf7de2007-03-19 01:24:52 +080035#ifdef CONFIG_POST
36#include <post.h>
37#endif
38
Aubrey Li26bf7de2007-03-19 01:24:52 +080039#define RXBUF_BASE_ADDR 0xFF900000
40#define TXBUF_BASE_ADDR 0xFF800000
41#define TX_BUF_CNT 1
42
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#define TOUT_LOOP 1000000
Aubrey Li26bf7de2007-03-19 01:24:52 +080044
Mike Frysinger6d7d4802009-01-08 11:57:57 -050045static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
46static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
Aubrey Li26bf7de2007-03-19 01:24:52 +080047static u16 txIdx; /* index of the current RX buffer */
48static u16 rxIdx; /* index of the current TX buffer */
49
Aubrey Li26bf7de2007-03-19 01:24:52 +080050/* DMAx_CONFIG values at DMA Restart */
Mike Frysinger6d7d4802009-01-08 11:57:57 -050051static const union {
52 u16 data;
53 ADI_DMA_CONFIG_REG reg;
54} txdmacfg = {
55 .reg = {
56 .b_DMA_EN = 1, /* enabled */
57 .b_WNR = 0, /* read from memory */
58 .b_WDSIZE = 2, /* wordsize is 32 bits */
59 .b_DMA2D = 0,
60 .b_RESTART = 0,
61 .b_DI_SEL = 0,
62 .b_DI_EN = 0, /* no interrupt */
63 .b_NDSIZE = 5, /* 5 half words is desc size */
64 .b_FLOW = 7 /* large desc flow */
65 },
Mike Frysinger395bce42008-02-24 23:58:13 -050066};
Aubrey Li26bf7de2007-03-19 01:24:52 +080067
Mike Frysingerac45af42008-10-14 04:52:00 -040068static int bfin_miiphy_wait(void)
69{
70 /* poll the STABUSY bit */
71 while (bfin_read_EMAC_STAADD() & STABUSY)
72 continue;
73 return 0;
74}
75
Joe Hershberger5a49f172016-08-08 11:28:38 -050076static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
Mike Frysingerac45af42008-10-14 04:52:00 -040077{
Joe Hershberger5a49f172016-08-08 11:28:38 -050078 ushort val = 0;
Mike Frysingerac45af42008-10-14 04:52:00 -040079 if (bfin_miiphy_wait())
80 return 1;
81 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
82 if (bfin_miiphy_wait())
83 return 1;
Joe Hershberger5a49f172016-08-08 11:28:38 -050084 val = bfin_read_EMAC_STADAT();
85 return val;
Mike Frysingerac45af42008-10-14 04:52:00 -040086}
87
Joe Hershberger5a49f172016-08-08 11:28:38 -050088static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
89 int reg, u16 val)
Mike Frysingerac45af42008-10-14 04:52:00 -040090{
91 if (bfin_miiphy_wait())
92 return 1;
93 bfin_write_EMAC_STADAT(val);
94 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
95 return 0;
96}
97
Mike Frysinger395bce42008-02-24 23:58:13 -050098int bfin_EMAC_initialize(bd_t *bis)
Aubrey Li26bf7de2007-03-19 01:24:52 +080099{
100 struct eth_device *dev;
Mike Frysingerac45af42008-10-14 04:52:00 -0400101 dev = malloc(sizeof(*dev));
Aubrey Li26bf7de2007-03-19 01:24:52 +0800102 if (dev == NULL)
103 hang();
104
105 memset(dev, 0, sizeof(*dev));
Mike Frysinger94060a12010-06-09 21:50:48 -0400106 strcpy(dev->name, "bfin_mac");
Aubrey Li26bf7de2007-03-19 01:24:52 +0800107
108 dev->iobase = 0;
109 dev->priv = 0;
110 dev->init = bfin_EMAC_init;
111 dev->halt = bfin_EMAC_halt;
112 dev->send = bfin_EMAC_send;
113 dev->recv = bfin_EMAC_recv;
Mike Frysinger4324dc72010-04-27 14:15:28 -0400114 dev->write_hwaddr = bfin_EMAC_setup_addr;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800115
116 eth_register(dev);
117
Mike Frysingerac45af42008-10-14 04:52:00 -0400118#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Joe Hershberger5a49f172016-08-08 11:28:38 -0500119 int retval;
120 struct mii_dev *mdiodev = mdio_alloc();
121 if (!mdiodev)
122 return -ENOMEM;
123 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
124 mdiodev->read = bfin_miiphy_read;
125 mdiodev->write = bfin_miiphy_write;
126
127 retval = mdio_register(mdiodev);
128 if (retval < 0)
129 return retval;
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500130
131 dev->priv = mdiodev;
Mike Frysingerac45af42008-10-14 04:52:00 -0400132#endif
133
Ben Warren91494732008-07-11 23:15:28 -0700134 return 0;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800135}
136
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000137static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800138{
139 int i;
140 int result = 0;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800141
142 if (length <= 0) {
143 printf("Ethernet: bad packet size: %d\n", length);
144 goto out;
145 }
146
Mike Frysinger0c714812010-07-25 16:38:12 -0400147 if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
Aubrey Li26bf7de2007-03-19 01:24:52 +0800148 printf("Ethernet: tx DMA error\n");
149 goto out;
150 }
151
Mike Frysinger0c714812010-07-25 16:38:12 -0400152 for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
Aubrey Li26bf7de2007-03-19 01:24:52 +0800153 if (i > TOUT_LOOP) {
154 puts("Ethernet: tx time out\n");
155 goto out;
156 }
157 }
158 txbuf[txIdx]->FrmData->NoBytes = length;
159 memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
160 txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
Mike Frysinger0c714812010-07-25 16:38:12 -0400161 bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
162 bfin_write_DMA2_CONFIG(txdmacfg.data);
163 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800164
165 for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
166 if (i > TOUT_LOOP) {
167 puts("Ethernet: tx error\n");
168 goto out;
169 }
170 }
171 result = txbuf[txIdx]->StatusWord;
172 txbuf[txIdx]->StatusWord = 0;
173 if ((txIdx + 1) >= TX_BUF_CNT)
174 txIdx = 0;
175 else
176 txIdx++;
Mike Frysinger395bce42008-02-24 23:58:13 -0500177 out:
Mike Frysinger8eed6ca2008-11-05 06:36:15 -0500178 debug("BFIN EMAC send: length = %d\n", length);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800179 return result;
180}
181
182static int bfin_EMAC_recv(struct eth_device *dev)
183{
184 int length = 0;
185
186 for (;;) {
187 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
188 length = -1;
189 break;
190 }
191 if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
192 printf("Ethernet: rx dma overrun\n");
193 break;
194 }
195 if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
196 printf("Ethernet: rx error\n");
197 break;
198 }
199 length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
200 if (length <= 4) {
201 printf("Ethernet: bad frame\n");
202 break;
203 }
Robin Getz488feef2009-08-24 10:33:39 -0400204
205 debug("%s: len = %d\n", __func__, length - 4);
206
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500207 net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
208 net_process_received_packet(net_rx_packets[rxIdx], length - 4);
Mike Frysinger0c714812010-07-25 16:38:12 -0400209 bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800210 rxbuf[rxIdx]->StatusWord = 0x00000000;
211 if ((rxIdx + 1) >= PKTBUFSRX)
212 rxIdx = 0;
213 else
214 rxIdx++;
215 }
216
217 return length;
218}
219
220/**************************************************************
221 *
222 * Ethernet Initialization Routine
223 *
224 *************************************************************/
225
Mike Frysingerac45af42008-10-14 04:52:00 -0400226/* MDC = SCLK / MDC_freq / 2 - 1 */
227#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
228
Mike Frysinger8339ad72010-06-02 05:56:22 -0400229#ifndef CONFIG_BFIN_MAC_PINS
230# ifdef CONFIG_RMII
231# define CONFIG_BFIN_MAC_PINS P_RMII0
232# else
233# define CONFIG_BFIN_MAC_PINS P_MII0
234# endif
235#endif
236
Mike Frysingerac45af42008-10-14 04:52:00 -0400237static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
238{
Mike Frysinger8339ad72010-06-02 05:56:22 -0400239 const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500240 int phydat;
Mike Frysingerac45af42008-10-14 04:52:00 -0400241 size_t count;
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500242 struct mii_dev *mdiodev = dev->priv;
Mike Frysingerac45af42008-10-14 04:52:00 -0400243
244 /* Enable PHY output */
Mike Frysinger0c714812010-07-25 16:38:12 -0400245 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
Mike Frysingerac45af42008-10-14 04:52:00 -0400246
247 /* Set all the pins to peripheral mode */
Mike Frysinger8339ad72010-06-02 05:56:22 -0400248 peripheral_request_list(pins, "bfin_mac");
Mike Frysingerac45af42008-10-14 04:52:00 -0400249
250 /* Odd word alignment for Receive Frame DMA word */
251 /* Configure checksum support and rcve frame word alignment */
Mike Frysingera7ec6ac2008-10-20 13:59:51 -0400252 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
Mike Frysingerac45af42008-10-14 04:52:00 -0400253
254 /* turn on auto-negotiation and wait for link to come up */
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500255 bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
256 BMCR_ANENABLE);
Mike Frysingerac45af42008-10-14 04:52:00 -0400257 count = 0;
258 while (1) {
259 ++count;
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500260 phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
261 MDIO_DEVAD_NONE, MII_BMSR);
262 if (phydat < 0)
263 return phydat;
Mike Frysingerac45af42008-10-14 04:52:00 -0400264 if (phydat & BMSR_LSTATUS)
265 break;
266 if (count > 30000) {
267 printf("%s: link down, check cable\n", dev->name);
268 return -1;
269 }
270 udelay(100);
271 }
272
273 /* see what kind of link we have */
Joe Hershberger875e0bc2016-08-08 11:28:40 -0500274 phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
275 MII_LPA);
276 if (phydat < 0)
277 return phydat;
Mike Frysingerac45af42008-10-14 04:52:00 -0400278 if (phydat & LPA_DUPLEX)
279 *opmode = FDMODE;
280 else
281 *opmode = 0;
282
283 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
Aaron Wu819ca382011-11-23 11:23:56 +0800284 bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
285 bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
Mike Frysingerac45af42008-10-14 04:52:00 -0400286
287 /* Initialize the TX DMA channel registers */
Mike Frysinger0c714812010-07-25 16:38:12 -0400288 bfin_write_DMA2_X_COUNT(0);
289 bfin_write_DMA2_X_MODIFY(4);
290 bfin_write_DMA2_Y_COUNT(0);
291 bfin_write_DMA2_Y_MODIFY(0);
Mike Frysingerac45af42008-10-14 04:52:00 -0400292
293 /* Initialize the RX DMA channel registers */
Mike Frysinger0c714812010-07-25 16:38:12 -0400294 bfin_write_DMA1_X_COUNT(0);
295 bfin_write_DMA1_X_MODIFY(4);
296 bfin_write_DMA1_Y_COUNT(0);
297 bfin_write_DMA1_Y_MODIFY(0);
Mike Frysingerac45af42008-10-14 04:52:00 -0400298
299 return 0;
300}
301
Mike Frysinger4324dc72010-04-27 14:15:28 -0400302static int bfin_EMAC_setup_addr(struct eth_device *dev)
303{
Mike Frysinger0c714812010-07-25 16:38:12 -0400304 bfin_write_EMAC_ADDRLO(
Mike Frysinger4324dc72010-04-27 14:15:28 -0400305 dev->enetaddr[0] |
306 dev->enetaddr[1] << 8 |
307 dev->enetaddr[2] << 16 |
Mike Frysinger0c714812010-07-25 16:38:12 -0400308 dev->enetaddr[3] << 24
309 );
310 bfin_write_EMAC_ADDRHI(
Mike Frysinger4324dc72010-04-27 14:15:28 -0400311 dev->enetaddr[4] |
Mike Frysinger0c714812010-07-25 16:38:12 -0400312 dev->enetaddr[5] << 8
313 );
Mike Frysinger4324dc72010-04-27 14:15:28 -0400314 return 0;
315}
316
Mike Frysinger395bce42008-02-24 23:58:13 -0500317static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800318{
319 u32 opmode;
320 int dat;
321 int i;
Mike Frysinger8eed6ca2008-11-05 06:36:15 -0500322 debug("Eth_init: ......\n");
Aubrey Li26bf7de2007-03-19 01:24:52 +0800323
324 txIdx = 0;
325 rxIdx = 0;
326
Mike Frysingerac45af42008-10-14 04:52:00 -0400327 /* Initialize System Register */
328 if (bfin_miiphy_init(dev, &dat) < 0)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800329 return -1;
330
Mike Frysingerac45af42008-10-14 04:52:00 -0400331 /* Initialize EMAC address */
Mike Frysinger4324dc72010-04-27 14:15:28 -0400332 bfin_EMAC_setup_addr(dev);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800333
Mike Frysingerac45af42008-10-14 04:52:00 -0400334 /* Initialize TX and RX buffer */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800335 for (i = 0; i < PKTBUFSRX; i++) {
336 rxbuf[i] = SetupRxBuffer(i);
337 if (i > 0) {
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500338 rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800339 if (i == (PKTBUFSRX - 1))
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500340 rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800341 }
342 }
343 for (i = 0; i < TX_BUF_CNT; i++) {
344 txbuf[i] = SetupTxBuffer(i);
345 if (i > 0) {
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500346 txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800347 if (i == (TX_BUF_CNT - 1))
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500348 txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800349 }
350 }
351
352 /* Set RX DMA */
Mike Frysinger0c714812010-07-25 16:38:12 -0400353 bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
354 bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800355
356 /* Wait MII done */
Mike Frysingerac45af42008-10-14 04:52:00 -0400357 bfin_miiphy_wait();
Aubrey Li26bf7de2007-03-19 01:24:52 +0800358
359 /* We enable only RX here */
360 /* ASTP : Enable Automatic Pad Stripping
361 PR : Promiscuous Mode for test
362 PSF : Receive frames with total length less than 64 bytes.
363 FDMODE : Full Duplex Mode
364 LB : Internal Loopback for test
365 RE : Receiver Enable */
366 if (dat == FDMODE)
367 opmode = ASTP | FDMODE | PSF;
368 else
369 opmode = ASTP | PSF;
370 opmode |= RE;
Mike Frysinger092d2482008-12-09 17:46:21 -0500371#ifdef CONFIG_RMII
Aubrey Li26bf7de2007-03-19 01:24:52 +0800372 opmode |= TE | RMII;
373#endif
374 /* Turn on the EMAC */
Mike Frysinger0c714812010-07-25 16:38:12 -0400375 bfin_write_EMAC_OPMODE(opmode);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800376 return 0;
377}
378
379static void bfin_EMAC_halt(struct eth_device *dev)
380{
Mike Frysinger8eed6ca2008-11-05 06:36:15 -0500381 debug("Eth_halt: ......\n");
Aubrey Li26bf7de2007-03-19 01:24:52 +0800382 /* Turn off the EMAC */
Mike Frysinger0c714812010-07-25 16:38:12 -0400383 bfin_write_EMAC_OPMODE(0);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800384 /* Turn off the EMAC RX DMA */
Mike Frysinger0c714812010-07-25 16:38:12 -0400385 bfin_write_DMA1_CONFIG(0);
386 bfin_write_DMA2_CONFIG(0);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800387}
388
Aubrey Li26bf7de2007-03-19 01:24:52 +0800389ADI_ETHER_BUFFER *SetupRxBuffer(int no)
390{
391 ADI_ETHER_FRAME_BUFFER *frmbuf;
392 ADI_ETHER_BUFFER *buf;
393 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
394 int total_size = nobytes_buffer + RECV_BUFSIZE;
395
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500396 buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
397 frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800398
399 memset(buf, 0x00, nobytes_buffer);
400 buf->FrmData = frmbuf;
401 memset(frmbuf, 0xfe, RECV_BUFSIZE);
402
403 /* set up first desc to point to receive frame buffer */
404 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
405 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
406 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
407 buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
408 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
409 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
410 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
411
412 /* set up second desc to point to status word */
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500413 buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800414 buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
415 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
416 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
417 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
418 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
419 buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
420 buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
421
422 return buf;
423}
424
425ADI_ETHER_BUFFER *SetupTxBuffer(int no)
426{
427 ADI_ETHER_FRAME_BUFFER *frmbuf;
428 ADI_ETHER_BUFFER *buf;
429 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
430 int total_size = nobytes_buffer + RECV_BUFSIZE;
431
Mike Frysinger6d7d4802009-01-08 11:57:57 -0500432 buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
433 frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800434
435 memset(buf, 0x00, nobytes_buffer);
436 buf->FrmData = frmbuf;
437 memset(frmbuf, 0x00, RECV_BUFSIZE);
438
439 /* set up first desc to point to receive frame buffer */
440 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
441 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
442 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
443 buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
444 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
445 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
446 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
447
448 /* set up second desc to point to status word */
449 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
450 buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
451 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
452 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
453 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
454 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
455 buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
456 buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
457
458 return buf;
459}
460
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800462int ether_post_test(int flags)
463{
464 uchar buf[64];
465 int i, value = 0;
466 int length;
Mike Frysinger0c714812010-07-25 16:38:12 -0400467 uint addr;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800468
469 printf("\n--------");
470 bfin_EMAC_init(NULL, NULL);
471 /* construct the package */
Mike Frysinger0c714812010-07-25 16:38:12 -0400472 addr = bfin_read_EMAC_ADDRLO();
473 buf[0] = buf[6] = addr;
474 buf[1] = buf[7] = addr >> 8;
475 buf[2] = buf[8] = addr >> 16;
476 buf[3] = buf[9] = addr >> 24;
477 addr = bfin_read_EMAC_ADDRHI();
478 buf[4] = buf[10] = addr;
479 buf[5] = buf[11] = addr >> 8;
Aubrey Li26bf7de2007-03-19 01:24:52 +0800480 buf[12] = 0x08; /* Type: ARP */
481 buf[13] = 0x06;
482 buf[14] = 0x00; /* Hardware type: Ethernet */
483 buf[15] = 0x01;
484 buf[16] = 0x08; /* Protocal type: IP */
485 buf[17] = 0x00;
486 buf[18] = 0x06; /* Hardware size */
487 buf[19] = 0x04; /* Protocol size */
488 buf[20] = 0x00; /* Opcode: request */
489 buf[21] = 0x01;
490
491 for (i = 0; i < 42; i++)
492 buf[i + 22] = i;
493 printf("--------Send 64 bytes......\n");
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000494 bfin_EMAC_send(NULL, buf, 64);
Aubrey Li26bf7de2007-03-19 01:24:52 +0800495 for (i = 0; i < 100; i++) {
496 udelay(10000);
497 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
498 value = 1;
499 break;
500 }
501 }
502 if (value == 0) {
503 printf("--------EMAC can't receive any data\n");
504 eth_halt();
505 return -1;
506 }
507 length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
508 for (i = 0; i < length; i++) {
509 if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
510 printf("--------EMAC receive error data!\n");
511 eth_halt();
512 return -1;
513 }
514 }
515 printf("--------receive %d bytes, matched\n", length);
516 bfin_EMAC_halt(NULL);
517 return 0;
518}
519#endif