blob: ac1c9b4780bb340ea9a943c8460d5a90f261bf25 [file] [log] [blame]
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050028#include <asm/mmu.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050029#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050031#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Andy Fleming09f3e092006-09-13 10:34:18 -050033#include <miiphy.h>
Kumar Galab90d2542007-11-29 00:11:44 -060034#include <libfdt.h>
35#include <fdt_support.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050036
37#include "../common/cadmus.h"
38#include "../common/eeprom.h"
Matthew McClintockbf1dfff2006-06-28 10:46:13 -050039#include "../common/via.h"
Jon Loeligerd9b94f22005-07-25 14:05:07 -050040
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050041DECLARE_GLOBAL_DATA_PTR;
42
Jon Loeligerd9b94f22005-07-25 14:05:07 -050043void local_bus_init(void);
44void sdram_init(void);
45
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046int checkboard (void)
47{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050050
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
53
Jon Loeligerd9b94f22005-07-25 14:05:07 -050054 uint cpu_board_rev = get_cpu_board_revision ();
55
56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 get_board_version (), pci_slot);
58
59 printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050062 /*
63 * Initialize local bus.
64 */
65 local_bus_init ();
66
Jon Loeligerd9b94f22005-07-25 14:05:07 -050067 /*
68 * Hack TSEC 3 and 4 IO voltages.
69 */
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
71
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050072 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050074 return 0;
75}
76
Becky Bruce9973e3c2008-06-09 16:03:40 -050077phys_size_t
Jon Loeligerd9b94f22005-07-25 14:05:07 -050078initdram(int board_type)
79{
80 long dram_size = 0;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050081
82 puts("Initializing\n");
83
84#if defined(CONFIG_DDR_DLL)
85 {
86 /*
87 * Work around to stabilize DDR DLL MSYNC_IN.
88 * Errata DDR9 seems to have been fixed.
89 * This is now the workaround for Errata DDR11:
90 * Override DLL = 1, Course Adj = 1, Tap Select = 0
91 */
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050094
95 gur->ddrdllcr = 0x81000000;
96 asm("sync;isync;msync");
97 udelay(200);
98 }
99#endif
Jon Loeligere31d2c12008-03-18 13:51:06 -0500100
101 dram_size = fsl_ddr_sdram();
102 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
103 dram_size *= 0x100000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500104
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500105 /*
106 * SDRAM Initialization
107 */
108 sdram_init();
109
110 puts(" DDR: ");
111 return dram_size;
112}
113
114/*
115 * Initialize Local Bus
116 */
117void
118local_bus_init(void)
119{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
121 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500122
123 uint clkdiv;
124 uint lbc_hz;
125 sys_info_t sysinfo;
126
127 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800128 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500129 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
130
131 gur->lbiuiplldcr1 = 0x00078080;
132 if (clkdiv == 16) {
133 gur->lbiuiplldcr0 = 0x7c0f1bf0;
134 } else if (clkdiv == 8) {
135 gur->lbiuiplldcr0 = 0x6c0f1bf0;
136 } else if (clkdiv == 4) {
137 gur->lbiuiplldcr0 = 0x5c0f1bf0;
138 }
139
140 lbc->lcrr |= 0x00030000;
141
142 asm("sync;isync;msync");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500143
144 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
145 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500146}
147
148/*
149 * Initialize SDRAM memory on the Local Bus.
150 */
151void
152sdram_init(void)
153{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500155
156 uint idx;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
158 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500159 uint cpu_board_rev;
160 uint lsdmr_common;
161
162 puts(" SDRAM: ");
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500165
166 /*
167 * Setup SDRAM Base and Option Registers
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 lbc->or2 = CONFIG_SYS_OR2_PRELIM;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500170 asm("msync");
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500173 asm("msync");
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500176 asm("msync");
177
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
180 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500181 asm("msync");
182
183 /*
184 * MPC8548 uses "new" 15-16 style addressing.
185 */
186 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500188 lsdmr_common |= LSDMR_BSMA1516;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500189
190 /*
191 * Issue PRECHARGE ALL command.
192 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500193 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500194 asm("sync;msync");
195 *sdram_addr = 0xff;
196 ppcDcbf((unsigned long) sdram_addr);
197 udelay(100);
198
199 /*
200 * Issue 8 AUTO REFRESH commands.
201 */
202 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500203 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500204 asm("sync;msync");
205 *sdram_addr = 0xff;
206 ppcDcbf((unsigned long) sdram_addr);
207 udelay(100);
208 }
209
210 /*
211 * Issue 8 MODE-set command.
212 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500213 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500214 asm("sync;msync");
215 *sdram_addr = 0xff;
216 ppcDcbf((unsigned long) sdram_addr);
217 udelay(100);
218
219 /*
220 * Issue NORMAL OP command.
221 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500222 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500223 asm("sync;msync");
224 *sdram_addr = 0xff;
225 ppcDcbf((unsigned long) sdram_addr);
226 udelay(200); /* Overkill. Must wait > 200 bus cycles */
227
228#endif /* enable SDRAM init */
229}
230
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500231#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500232/* For some reason the Tundra PCI bridge shows up on itself as a
233 * different device. Work around that by refusing to configure it.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500234 */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500235void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500236
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500237static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500238 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700239 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
240 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600241 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700242 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
243 mpc85xx_config_via_usb, {0,0,0}},
244 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
245 mpc85xx_config_via_usb2, {0,0,0}},
246 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600247 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700248 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
249 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600250 {},
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500251};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500252
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500253static struct pci_controller pci1_hose = {
254 config_table: pci_mpc85xxcds_config_table};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500255#endif /* CONFIG_PCI */
256
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500257#ifdef CONFIG_PCI2
258static struct pci_controller pci2_hose;
259#endif /* CONFIG_PCI2 */
260
261#ifdef CONFIG_PCIE1
262static struct pci_controller pcie1_hose;
263#endif /* CONFIG_PCIE1 */
264
265int first_free_busno=0;
266
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500267void
268pci_init_board(void)
269{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500271 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
272 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
273
274
275#ifdef CONFIG_PCI1
276{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500278 struct pci_controller *hose = &pci1_hose;
279 struct pci_config_table *table;
Kumar Gala2dba0de2008-10-21 08:28:33 -0500280 struct pci_region *r = hose->regions;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500281
282 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
283 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
284 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
285
286 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
287
288 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
289
290 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
291 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
292 (pci_32) ? 32 : 64,
293 (pci_speed == 33333000) ? "33" :
294 (pci_speed == 66666000) ? "66" : "unknown",
295 pci_clk_sel ? "sync" : "async",
296 pci_agent ? "agent" : "host",
297 pci_arb ? "arbiter" : "external-arbiter"
298 );
299
300
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500301 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500302 r += fsl_pci_setup_inbound_windows(r);
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500303
304 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500305 pci_set_region(r++,
Kumar Gala10795f42008-12-02 16:08:36 -0600306 CONFIG_SYS_PCI1_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 CONFIG_SYS_PCI1_MEM_PHYS,
308 CONFIG_SYS_PCI1_MEM_SIZE,
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500309 PCI_REGION_MEM);
310
311 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500312 pci_set_region(r++,
Kumar Gala5f91ef62008-12-02 16:08:37 -0600313 CONFIG_SYS_PCI1_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314 CONFIG_SYS_PCI1_IO_PHYS,
315 CONFIG_SYS_PCI1_IO_SIZE,
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500316 PCI_REGION_IO);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500317 hose->region_count = r - hose->regions;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500318
319 /* relocate config table pointers */
320 hose->config_table = \
321 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
322 for (table = hose->config_table; table && table->vendor; table++)
323 table->config_device += gd->reloc_off;
324
325 hose->first_busno=first_free_busno;
326 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
327
328 fsl_pci_init(hose);
329 first_free_busno=hose->last_busno+1;
330 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
331#ifdef CONFIG_PCIX_CHECK
Peter Tyser9427ccd2008-12-01 13:47:12 -0600332 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500333 /* PCI-X init */
334 if (CONFIG_SYS_CLK_FREQ < 66000000)
335 printf("PCI-X will only work at 66 MHz\n");
336
337 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
338 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
339 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
340 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500341#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500342 } else {
343 printf (" PCI: disabled\n");
344 }
345}
346#else
347 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
348#endif
349
350#ifdef CONFIG_PCI2
351{
352 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
353 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
354 if (pci_dual) {
355 printf (" PCI2: 32 bit, 66 MHz, %s\n",
356 pci2_clk_sel ? "sync" : "async");
357 } else {
358 printf (" PCI2: disabled\n");
359 }
360}
361#else
362 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
363#endif /* CONFIG_PCI2 */
364
365#ifdef CONFIG_PCIE1
366{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500368 struct pci_controller *hose = &pcie1_hose;
369 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500370 struct pci_region *r = hose->regions;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500371
372 int pcie_configured = io_sel >= 1;
373
374 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
375 printf ("\n PCIE connected to slot as %s (base address %x)",
376 pcie_ep ? "End Point" : "Root Complex",
377 (uint)pci);
378
379 if (pci->pme_msg_det) {
380 pci->pme_msg_det = 0xffffffff;
381 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
382 }
383 printf ("\n");
384
385 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500386 r += fsl_pci_setup_inbound_windows(r);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500387
388 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500389 pci_set_region(r++,
Kumar Gala10795f42008-12-02 16:08:36 -0600390 CONFIG_SYS_PCIE1_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391 CONFIG_SYS_PCIE1_MEM_PHYS,
392 CONFIG_SYS_PCIE1_MEM_SIZE,
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500393 PCI_REGION_MEM);
394
395 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500396 pci_set_region(r++,
Kumar Gala5f91ef62008-12-02 16:08:37 -0600397 CONFIG_SYS_PCIE1_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398 CONFIG_SYS_PCIE1_IO_PHYS,
399 CONFIG_SYS_PCIE1_IO_SIZE,
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500400 PCI_REGION_IO);
401
Kumar Gala2dba0de2008-10-21 08:28:33 -0500402 hose->region_count = r - hose->regions;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500403
404 hose->first_busno=first_free_busno;
405 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
406
407 fsl_pci_init(hose);
408 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
409
410 first_free_busno=hose->last_busno+1;
411
412 } else {
413 printf (" PCIE: disabled\n");
414 }
415 }
416#else
417 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
418#endif
419
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500420}
Andy Fleming09f3e092006-09-13 10:34:18 -0500421
422int last_stage_init(void)
423{
Jon Loeligerf5012822006-10-20 15:54:34 -0500424 unsigned short temp;
Andy Fleming09f3e092006-09-13 10:34:18 -0500425
426 /* Change the resistors for the PHY */
427 /* This is needed to get the RGMII working for the 1.3+
428 * CDS cards */
429 if (get_board_version() == 0x13) {
Kim Phillips255a35772007-05-16 16:52:19 -0500430 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500431 TSEC1_PHY_ADDR, 29, 18);
432
Kim Phillips255a35772007-05-16 16:52:19 -0500433 miiphy_read(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500434 TSEC1_PHY_ADDR, 30, &temp);
435
436 temp = (temp & 0xf03f);
437 temp |= 2 << 9; /* 36 ohm */
438 temp |= 2 << 6; /* 39 ohm */
439
Kim Phillips255a35772007-05-16 16:52:19 -0500440 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500441 TSEC1_PHY_ADDR, 30, temp);
442
Kim Phillips255a35772007-05-16 16:52:19 -0500443 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500444 TSEC1_PHY_ADDR, 29, 3);
445
Kim Phillips255a35772007-05-16 16:52:19 -0500446 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500447 TSEC1_PHY_ADDR, 30, 0x8000);
448 }
449
450 return 0;
451}
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500452
453
Kumar Galab90d2542007-11-29 00:11:44 -0600454#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500455void ft_pci_setup(void *blob, bd_t *bd)
456{
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500457#ifdef CONFIG_PCI1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500458 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500459#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500460#ifdef CONFIG_PCIE1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500461 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500462#endif
463}
464#endif