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robert lazarski7bd61042007-12-21 10:36:37 -05001/*
2 * Copyright 2007
3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
4 *
5 * Copyright 2004, 2007 Freescale Semiconductor.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * atum8548 board configuration file
28 *
29 * Please refer to doc/README.atum8548 for more info.
30 *
31 */
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/* Debug Options, Disable in production
36#define ET_DEBUG 1
37#define CONFIG_PANIC_HANG 1
38#define DEBUG 1
39*/
40
41/* CPLD Configuration Options */
42#define MPC85xx_ATUM_CLKOCR 0x80000002
43
44/* High Level Configuration Options */
45#define CONFIG_BOOKE 1 /* BOOKE */
46#define CONFIG_E500 1 /* BOOKE e500 family */
47#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
48#define CONFIG_MPC8548 1 /* MPC8548 specific */
49
50#define CONFIG_PCI 1 /* enable any pci type devices */
51#define CONFIG_PCI1 1 /* PCI controller 1 */
52#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
53#define CONFIG_PCI2 1 /* PCI controller 2 */
54#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
55
56#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
57#define CONFIG_ENV_OVERWRITE
robert lazarski7bd61042007-12-21 10:36:37 -050058
robert lazarski7bd61042007-12-21 10:36:37 -050059#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
60
Kumar Gala4d3521c2008-01-16 09:15:29 -060061#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
62
robert lazarski7bd61042007-12-21 10:36:37 -050063#define CONFIG_SYS_CLK_FREQ 33000000
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
robert lazarski7bd61042007-12-21 10:36:37 -050070
71/*
72 * Only possible on E500 Version 2 or newer cores.
73 */
74#define CONFIG_ENABLE_36BIT_PHYS 1
75
76#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
77
Wolfgang Denk53677ef2008-05-20 16:00:29 +020078#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
robert lazarski7bd61042007-12-21 10:36:37 -050079#define CONFIG_ENABLE_36BIT_PHYS 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#undef CONFIG_SYS_DRAM_TEST
81#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x00400000
robert lazarski7bd61042007-12-21 10:36:37 -050083
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
90#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
91#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
robert lazarski7bd61042007-12-21 10:36:37 -050092
93#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
robert lazarski7bd61042007-12-21 10:36:37 -050094
Kumar Galaa947e4c2008-08-26 23:14:14 -050095/* DDR Setup */
96#define CONFIG_FSL_DDR2
97#undef CONFIG_FSL_DDR_INTERACTIVE
98#define CONFIG_DDR_ECC /* only for ECC DDR module */
99#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
100#define CONFIG_DDR_SPD
101
102#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galaa947e4c2008-08-26 23:14:14 -0500107#define CONFIG_VERY_BIG_RAM
robert lazarski7bd61042007-12-21 10:36:37 -0500108
Kumar Galaa947e4c2008-08-26 23:14:14 -0500109#define CONFIG_NUM_DDR_CONTROLLERS 1
110#define CONFIG_DIMM_SLOTS_PER_CTLR 1
111#define CONFIG_CHIP_SELECTS_PER_CTRL 2
robert lazarski7bd61042007-12-21 10:36:37 -0500112
Kumar Galaa947e4c2008-08-26 23:14:14 -0500113/* I2C addresses of SPD EEPROMs */
114#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
115
116/* Manually set up DDR parameters */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
118#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
119#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
120#define CONFIG_SYS_DDR_TIMING_0 0x00260802
121#define CONFIG_SYS_DDR_TIMING_1 0x38355322
122#define CONFIG_SYS_DDR_TIMING_2 0x039048c7
123#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
124#define CONFIG_SYS_DDR_MODE 0x00000432
125#define CONFIG_SYS_DDR_INTERVAL 0x05150100
Kumar Galaa947e4c2008-08-26 23:14:14 -0500126#define DDR_SDRAM_CFG 0x43000000
robert lazarski7bd61042007-12-21 10:36:37 -0500127
128#undef CONFIG_CLOCKS_IN_MHZ
129
130/*
131 * Local Bus Definitions
132 */
133
134/*
135 * FLASH on the Local Bus
136 * based on flash chip S29GL01GP
137 * One bank, 128M, using the CFI driver.
138 * Boot from BR0 bank at 0xf800_0000
139 *
140 * BR0:
141 * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
142 * Port Size = 16 bits = BRx[19:20] = 10
143 * Use GPCM = BRx[24:26] = 000
144 * Valid = BRx[31] = 1
145 *
146 * 0 4 8 12 16 20 24 28
147 * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
148 *
149 * OR0:
150 * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
151 * Reserved ORx[17:18] = 00
152 * CSNT = ORx[20] = 1
153 * ACS = half cycle delay = ORx[21:22] = 11
154 * SCY = 6 = ORx[24:27] = 0110
155 * TRLX = use relaxed timing = ORx[29] = 1
156 * EAD = use external address latch delay = OR[31] = 1
157 *
158 * 0 4 8 12 16 20 24 28
159 * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
160 */
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
163#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
robert lazarski7bd61042007-12-21 10:36:37 -0500164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BR0_PRELIM 0xf8001001
robert lazarski7bd61042007-12-21 10:36:37 -0500166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_OR0_PRELIM 0xf8000E65
robert lazarski7bd61042007-12-21 10:36:37 -0500168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
170#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
171#undef CONFIG_SYS_FLASH_CHECKSUM
172#define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
173#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
robert lazarski7bd61042007-12-21 10:36:37 -0500174
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
robert lazarski7bd61042007-12-21 10:36:37 -0500177
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200178#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_CFI 1
180#define CONFIG_SYS_FLASH_EMPTY_INFO
robert lazarski7bd61042007-12-21 10:36:37 -0500181
182/*
183 * Flash on the LocalBus
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
robert lazarski7bd61042007-12-21 10:36:37 -0500186
187/* Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_RAM_LOCK 1
189#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
190#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
robert lazarski7bd61042007-12-21 10:36:37 -0500191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
robert lazarski7bd61042007-12-21 10:36:37 -0500193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
195#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
robert lazarski7bd61042007-12-21 10:36:37 -0500197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
robert lazarski7bd61042007-12-21 10:36:37 -0500200
201/* Serial Port */
202#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_NS16550
204#define CONFIG_SYS_NS16550_SERIAL
205#define CONFIG_SYS_NS16550_REG_SIZE 1
206#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
robert lazarski7bd61042007-12-21 10:36:37 -0500207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_BAUDRATE_TABLE \
robert lazarski7bd61042007-12-21 10:36:37 -0500209 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
212#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
robert lazarski7bd61042007-12-21 10:36:37 -0500213
214/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_HUSH_PARSER
216#ifdef CONFIG_SYS_HUSH_PARSER
217#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
robert lazarski7bd61042007-12-21 10:36:37 -0500218#endif
219
220/* pass open firmware flat tree */
221#define CONFIG_OF_LIBFDT 1
222#define CONFIG_OF_BOARD_SETUP 1
223
224/*
225 * I2C
226 */
227#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
228#define CONFIG_HARD_I2C /* I2C with hardware support*/
229#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
231#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
232#define CONFIG_SYS_I2C_SLAVE 0x7F
233#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
234#define CONFIG_SYS_I2C_OFFSET 0x3000
robert lazarski7bd61042007-12-21 10:36:37 -0500235
236/*
237 * General PCI
238 * Memory space is mapped 1-1, but I/O space must start from 0.
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
robert lazarski7bd61042007-12-21 10:36:37 -0500241
Kumar Galafeadd5d2009-11-04 11:05:02 -0600242#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
243#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galafeadd5d2009-11-04 11:05:02 -0600245#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
247#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
robert lazarski7bd61042007-12-21 10:36:37 -0500248
249#ifdef CONFIG_PCI2
Kumar Galafeadd5d2009-11-04 11:05:02 -0600250#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
251#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galafeadd5d2009-11-04 11:05:02 -0600253#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
255#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
robert lazarski7bd61042007-12-21 10:36:37 -0500256#endif
257
258#ifdef CONFIG_PCIE1
Kumar Galafeadd5d2009-11-04 11:05:02 -0600259#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
260#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galafeadd5d2009-11-04 11:05:02 -0600262#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
264#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
robert lazarski7bd61042007-12-21 10:36:37 -0500265#endif
266
267
268#if !defined(CONFIG_PCI_PNP)
269 #define PCI_ENET0_IOADDR 0xe0000000
270 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200271 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
robert lazarski7bd61042007-12-21 10:36:37 -0500272#endif
273
274#if defined(CONFIG_PCI)
275
276#define CONFIG_NET_MULTI
277#define CONFIG_PCI_PNP /* do pci plug-and-play */
278
279#undef CONFIG_EEPRO100
280#undef CONFIG_TULIP
281
282#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
283
robert lazarski7bd61042007-12-21 10:36:37 -0500284#endif /* CONFIG_PCI */
285
286#if defined(CONFIG_TSEC_ENET)
287
288#ifndef CONFIG_NET_MULTI
289#define CONFIG_NET_MULTI 1
290#endif
291
292#define CONFIG_MII 1 /* MII PHY management */
293#define CONFIG_TSEC1 1
294#define CONFIG_TSEC1_NAME "eTSEC0"
295#define CONFIG_TSEC2 1
296#define CONFIG_TSEC2_NAME "eTSEC1"
297#define CONFIG_TSEC3 1
298#define CONFIG_TSEC3_NAME "eTSEC2"
299#define CONFIG_TSEC4 1
300#define CONFIG_TSEC4_NAME "eTSEC3"
301#undef CONFIG_MPC85XX_FEC
302
303#define TSEC1_PHY_ADDR 0
304#define TSEC2_PHY_ADDR 1
305#define TSEC3_PHY_ADDR 2
306#define TSEC4_PHY_ADDR 3
307
308#define TSEC1_PHYIDX 0
309#define TSEC2_PHYIDX 0
310#define TSEC3_PHYIDX 0
311#define TSEC4_PHYIDX 0
312#define TSEC1_FLAGS TSEC_GIGABIT
313#define TSEC2_FLAGS TSEC_GIGABIT
314#define TSEC3_FLAGS TSEC_GIGABIT
315#define TSEC4_FLAGS TSEC_GIGABIT
316
317/* Options are: eTSEC[0-3] */
318#define CONFIG_ETHPRIME "eTSEC2"
319#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
320#endif /* CONFIG_TSEC_ENET */
321
322/*
323 * Environment
324 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200325#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200327#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
328#define CONFIG_ENV_SIZE 0x2000
robert lazarski7bd61042007-12-21 10:36:37 -0500329
330#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
robert lazarski7bd61042007-12-21 10:36:37 -0500332
333/*
334 * BOOTP options
335 */
336#define CONFIG_BOOTP_BOOTFILESIZE
337#define CONFIG_BOOTP_BOOTPATH
338#define CONFIG_BOOTP_GATEWAY
339#define CONFIG_BOOTP_HOSTNAME
340
341
342/*
343 * Command line configuration.
344 */
345#include <config_cmd_default.h>
346
347#define CONFIG_CMD_PING
348#define CONFIG_CMD_I2C
349#define CONFIG_CMD_MII
350
351#if defined(CONFIG_PCI)
352 #define CONFIG_CMD_PCI
353#endif
354
355
356#undef CONFIG_WATCHDOG /* watchdog disabled */
357
358/*
359 * Miscellaneous configurable options
360 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_LONGHELP /* undef to save memory */
362#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
363#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
robert lazarski7bd61042007-12-21 10:36:37 -0500364#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
robert lazarski7bd61042007-12-21 10:36:37 -0500366#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
robert lazarski7bd61042007-12-21 10:36:37 -0500368#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
370#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
371#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
372#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
robert lazarski7bd61042007-12-21 10:36:37 -0500373
374/*
375 * For booting Linux, the board info and command line data
376 * have to be in the first 8 MB of memory, since this is
377 * the maximum mapped by the Linux kernel during initialization.
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
robert lazarski7bd61042007-12-21 10:36:37 -0500380
robert lazarski7bd61042007-12-21 10:36:37 -0500381/*
382 * Internal Definitions
383 *
384 * Boot Flags
385 */
386#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
387#define BOOTFLAG_WARM 0x02 /* Software reboot */
388
389#if defined(CONFIG_CMD_KGDB)
390#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
391#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
392#endif
393
394/*
395 * Environment Configuration
396 */
397
398/* The mac addresses for all ethernet interface */
399#if defined(CONFIG_TSEC_ENET)
400#define CONFIG_HAS_ETH0
401#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
402#define CONFIG_HAS_ETH1
403#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
404#define CONFIG_HAS_ETH2
405#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
406#define CONFIG_HAS_ETH3
407#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
408#endif
409
410#define CONFIG_IPADDR 10.101.43.142
411
412#define CONFIG_HOSTNAME atum
413#define CONFIG_ROOTPATH /nfsroot
414#define CONFIG_BOOTFILE /tftpboot/uImage.atum
415#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
416
417#define CONFIG_SERVERIP 10.101.43.10
418#define CONFIG_GATEWAYIP 10.101.45.1
419#define CONFIG_NETMASK 255.255.248.0
420
421#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
422
423#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
424#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
425
426#define CONFIG_BAUDRATE 115200
427
428#define CONFIG_NFSBOOTCOMMAND \
429 "setenv bootargs root=/dev/nfs rw " \
430 "nfsroot=$serverip:$rootpath " \
431 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
432 "console=$consoledev,$baudrate $othbootargs;" \
433 "tftp $loadaddr $bootfile;" \
434 "tftp $dtbaddr $dtbfile;" \
435 "bootm $loadaddr - $dtbaddr"
436
437
438#define CONFIG_RAMBOOTCOMMAND \
439 "setenv bootargs root=/dev/ram rw " \
440 "console=$consoledev,$baudrate $othbootargs;" \
441 "tftp $ramdiskaddr $ramdiskfile;" \
442 "tftp $loadaddr $bootfile;" \
443 "tftp $dtbaddr $dtbfile;" \
444 "bootm $loadaddr $ramdiskaddr $dtbaddr"
445
446#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
447
448#endif /* __CONFIG_H */