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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach2da0fc02011-01-21 09:31:21 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibach2da0fc02011-01-21 09:31:21 +010012#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME dlvsion-10g
Dirk Eibachcccd4f42014-07-03 09:28:20 +020020#define CONFIG_IDENT_STRING " dlvision-10g 0.06"
Dirk Eibach2da0fc02011-01-21 09:31:21 +010021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibachb19bf832012-04-26 03:54:23 +000025#define CONFIG_MISC_INIT_R
Dirk Eibach2da0fc02011-01-21 09:31:21 +010026#define CONFIG_LAST_STAGE_INIT
27
28#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
29
30/*
31 * Configure PLL
32 */
33#define PLLMR0_DEFAULT PLLMR0_266_133_66
34#define PLLMR1_DEFAULT PLLMR1_266_133_66
35
36/* new uImage format support */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020037#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibach2da0fc02011-01-21 09:31:21 +010038
39#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
40
41/*
42 * Default environment variables
43 */
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 CONFIG_AMCC_DEF_ENV \
46 CONFIG_AMCC_DEF_ENV_POWERPC \
47 CONFIG_AMCC_DEF_ENV_NOR_UPD \
48 "kernel_addr=fc000000\0" \
49 "fdt_addr=fc1e0000\0" \
50 "ramdisk_addr=fc200000\0" \
51 ""
52
53#define CONFIG_PHY_ADDR 4 /* PHY address */
54#define CONFIG_HAS_ETH0
55#define CONFIG_HAS_ETH1
56#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
57#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
58
59/*
60 * Commands additional to the ones defined in amcc-common.h
61 */
Dirk Eibachb19bf832012-04-26 03:54:23 +000062#define CONFIG_CMD_DTT
Dirk Eibach4fb9b412014-07-03 09:28:25 +020063#undef CONFIG_CMD_DIAG
Dirk Eibach2da0fc02011-01-21 09:31:21 +010064#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020065#undef CONFIG_CMD_IRQ
Dirk Eibach2da0fc02011-01-21 09:31:21 +010066
67/*
68 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
69 */
70#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
71
72/* SDRAM timings used in datasheet */
73#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
74#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
75#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
76#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
77#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
78
79/*
80 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
81 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
82 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
83 * The Linux BASE_BAUD define should match this configuration.
84 * baseBaud = cpuClock/(uartDivisor*16)
85 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
86 * set Linux BASE_BAUD to 403200.
87 */
88#define CONFIG_CONS_INDEX 1 /* Use UART0 */
89#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
90#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
91#define CONFIG_SYS_BASE_BAUD 691200
92
93/*
94 * I2C stuff
95 */
Dirk Eibache3135362014-07-03 09:28:19 +020096#define CONFIG_SYS_I2C_PPC4XX
97#define CONFIG_SYS_I2C_PPC4XX_CH0
Dirk Eibach880540d2013-04-25 02:40:01 +000098#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibache3135362014-07-03 09:28:19 +020099#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100100
Dirk Eibachb46226b2014-07-03 09:28:18 +0200101#define CONFIG_SYS_I2C_IHS
Dirk Eibache1d11272015-10-28 11:46:28 +0100102#define CONFIG_SYS_I2C_IHS_DUAL
Dirk Eibachb46226b2014-07-03 09:28:18 +0200103#define CONFIG_SYS_I2C_IHS_CH0
104#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
105#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
Dirk Eibache1d11272015-10-28 11:46:28 +0100106#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
107#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200108#define CONFIG_SYS_I2C_IHS_CH1
109#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
110#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
Dirk Eibache1d11272015-10-28 11:46:28 +0100111#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
112#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200113
Dirk Eibache1d11272015-10-28 11:46:28 +0100114#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibachb46226b2014-07-03 09:28:18 +0200115
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100116/* Temp sensor/hwmon/dtt */
Dirk Eibache1d11272015-10-28 11:46:28 +0100117#define CONFIG_SYS_DTT_BUS_NUM 4
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100118#define CONFIG_DTT_LM63 1 /* National LM63 */
Dirk Eibach2ade7be2012-04-26 03:54:24 +0000119#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100120#define CONFIG_DTT_PWM_LOOKUPTABLE \
Dirk Eibach97ca7b32011-10-04 11:13:53 +0200121 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
122 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100123#define CONFIG_DTT_TACH_LIMIT 0xa10
124
Dirk Eibache1d11272015-10-28 11:46:28 +0100125#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
126#define CONFIG_SYS_SIL1178_I2C {0, 2}
127#define CONFIG_SYS_DP501_I2C {0, 2}
Dirk Eibache3135362014-07-03 09:28:19 +0200128
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100129/* EBC peripherals */
130
131#define CONFIG_SYS_FLASH_BASE 0xFC000000
132#define CONFIG_SYS_FPGA0_BASE 0x7f100000
133#define CONFIG_SYS_FPGA1_BASE 0x7f200000
134#define CONFIG_SYS_LATCH_BASE 0x7f300000
135
136#define CONFIG_SYS_FPGA_BASE(k) \
137 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
138
139#define CONFIG_SYS_FPGA_DONE(k) \
140 (k ? 0x2000 : 0x1000)
141
142#define CONFIG_SYS_FPGA_COUNT 2
143
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200144#define CONFIG_SYS_FPGA_PTR { \
145 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
146 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
147
148#define CONFIG_SYS_FPGA_COMMON
149
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100150#define CONFIG_SYS_LATCH0_RESET 0xffff
151#define CONFIG_SYS_LATCH0_BOOT 0xffff
Dirk Eibach3e24dd22013-08-09 10:52:54 +0200152#define CONFIG_SYS_LATCH1_RESET 0xffbf
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100153#define CONFIG_SYS_LATCH1_BOOT 0xffff
154
Dirk Eibach5cb41002011-04-06 13:53:46 +0200155#define CONFIG_SYS_FPGA_NO_RFL_HI
156
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100157/*
158 * FLASH organization
159 */
160#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
161#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
162
163#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
166#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
167
168#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
169#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
170
171#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100172
173#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
174#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
175
176#ifdef CONFIG_ENV_IS_IN_FLASH
177#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
178#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
179#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
180
181/* Address and size of Redundant Environment Sector */
182#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
183#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
184#endif
185
186/*
187 * PPC405 GPIO Configuration
188 */
189#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
190{ \
191/* GPIO Core 0 */ \
192{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
193{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
194{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
195{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
196{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
197{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
198{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
199{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
200{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
201{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
202{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
207{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
209{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
210{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
211{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
212{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
214{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
215{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
216{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
217{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
218{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
220{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
221{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
222{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
223{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
224} \
225}
226
227/*
228 * Definitions for initial stack pointer and data area (in data cache)
229 */
230/* use on chip memory (OCM) for temperary stack until sdram is tested */
231#define CONFIG_SYS_TEMP_STACK_OCM 1
232
233/* On Chip Memory location */
234#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
235#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
236#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
York Sunb39d1212016-04-06 13:22:10 -0700237#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100238
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100239#define CONFIG_SYS_GBL_DATA_OFFSET \
York Sunb39d1212016-04-06 13:22:10 -0700240 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242
243/*
244 * External Bus Controller (EBC) Setup
245 */
246
247/* Memory Bank 0 (NOR-flash) */
248#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
249 EBC_BXAP_FWT_ENCODE(8) | \
250 EBC_BXAP_BWT_ENCODE(7) | \
251 EBC_BXAP_BCE_DISABLE | \
252 EBC_BXAP_BCT_2TRANS | \
253 EBC_BXAP_CSN_ENCODE(0) | \
254 EBC_BXAP_OEN_ENCODE(2) | \
255 EBC_BXAP_WBN_ENCODE(2) | \
256 EBC_BXAP_WBF_ENCODE(2) | \
257 EBC_BXAP_TH_ENCODE(4) | \
258 EBC_BXAP_RE_DISABLED | \
259 EBC_BXAP_SOR_NONDELAYED | \
260 EBC_BXAP_BEM_WRITEONLY | \
261 EBC_BXAP_PEN_DISABLED)
262#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
263 EBC_BXCR_BS_64MB | \
264 EBC_BXCR_BU_RW | \
265 EBC_BXCR_BW_16BIT)
266
267/* Memory Bank 1 (FPGA0) */
268#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
269 EBC_BXAP_TWT_ENCODE(5) | \
270 EBC_BXAP_BCE_DISABLE | \
271 EBC_BXAP_BCT_2TRANS | \
272 EBC_BXAP_CSN_ENCODE(0) | \
273 EBC_BXAP_OEN_ENCODE(2) | \
274 EBC_BXAP_WBN_ENCODE(1) | \
275 EBC_BXAP_WBF_ENCODE(1) | \
276 EBC_BXAP_TH_ENCODE(0) | \
277 EBC_BXAP_RE_DISABLED | \
278 EBC_BXAP_SOR_NONDELAYED | \
279 EBC_BXAP_BEM_WRITEONLY | \
280 EBC_BXAP_PEN_DISABLED)
281#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
282 EBC_BXCR_BS_1MB | \
283 EBC_BXCR_BU_RW | \
284 EBC_BXCR_BW_16BIT)
285
286/* Memory Bank 2 (FPGA1) */
287#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
288 EBC_BXAP_TWT_ENCODE(6) | \
289 EBC_BXAP_BCE_DISABLE | \
290 EBC_BXAP_BCT_2TRANS | \
291 EBC_BXAP_CSN_ENCODE(0) | \
292 EBC_BXAP_OEN_ENCODE(2) | \
293 EBC_BXAP_WBN_ENCODE(1) | \
294 EBC_BXAP_WBF_ENCODE(1) | \
295 EBC_BXAP_TH_ENCODE(0) | \
296 EBC_BXAP_RE_DISABLED | \
297 EBC_BXAP_SOR_NONDELAYED | \
298 EBC_BXAP_BEM_WRITEONLY | \
299 EBC_BXAP_PEN_DISABLED)
300#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
301 EBC_BXCR_BS_1MB | \
302 EBC_BXCR_BU_RW | \
303 EBC_BXCR_BW_16BIT)
304
305/* Memory Bank 3 (Latches) */
306#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
307 EBC_BXAP_FWT_ENCODE(8) | \
308 EBC_BXAP_BWT_ENCODE(4) | \
309 EBC_BXAP_BCE_DISABLE | \
310 EBC_BXAP_BCT_2TRANS | \
311 EBC_BXAP_CSN_ENCODE(0) | \
312 EBC_BXAP_OEN_ENCODE(1) | \
313 EBC_BXAP_WBN_ENCODE(1) | \
314 EBC_BXAP_WBF_ENCODE(1) | \
315 EBC_BXAP_TH_ENCODE(2) | \
316 EBC_BXAP_RE_DISABLED | \
317 EBC_BXAP_SOR_NONDELAYED | \
318 EBC_BXAP_BEM_WRITEONLY | \
319 EBC_BXAP_PEN_DISABLED)
320#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
321 EBC_BXCR_BS_1MB | \
322 EBC_BXCR_BU_RW | \
323 EBC_BXCR_BW_16BIT)
324
325/*
326 * OSD Setup
327 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200328#define CONFIG_SYS_MPC92469AC
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100329#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
Dirk Eibache1d11272015-10-28 11:46:28 +0100330#define CONFIG_SYS_DP501_DIFFERENTIAL
331#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100332
333#endif /* __CONFIG_H */