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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 720ba46e71b09d379a3590a4a35c35d5938338b5 / . / board / gdsys / gdppc440etx / init.S
blob: 2db84b59a1e39a42396c22956ea6eb21d713a0f7 [file] [log] [blame]
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]1/*
2* (C) Copyright 2008
3* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4*
5* based on board/amcc/yosemite/init.S
6* original Copyright not specified there
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]8*/
9
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]11#include <ppc_asm.tmpl>
12#include <config.h>
13
14#include <asm/mmu.h>
15
16/**************************************************************************
17 * TLB TABLE
18 *
19 * This table is used by the cpu boot code to setup the initial tlb
20 * entries. Rather than make broad assumptions in the cpu source tree,
21 * this table lets each board set things up however they like.
22 *
23 * Pointer to the table is returned in r1
24 *
25 *************************************************************************/
26
27 .section .bootpg,"ax"
28 .globl tlbtab
29
30tlbtab:
31 tlbtab_start
32
33 /*
34 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
35 * the speed up boot process. It is patched after relocation to enable SA_I
36 */
37 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]38 0, AC_RWX | SA_G/*|SA_I*/)
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]39
40 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
41 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]42 0, AC_RWX | SA_G )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]43
44 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]45 0, AC_RWX | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]46 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]47 0, AC_RW | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]48
49 /* PCI */
50 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]51 0, AC_RW | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]52 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]53 0, AC_RW | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]54 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]55 0, AC_RW | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]56 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]57 0, AC_RW | SA_IG )
Dirk Eibach89b86192008-12-09 13:12:40 +0100[diff] [blame]58
59 tlbtab_end