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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8260.h>
26#include <asm/processor.h>
27
Heiko Schocherfa230442006-12-21 17:17:02 +010028#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
29extern unsigned long board_get_cpu_clk_f (void);
30#endif
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenk4a9cbbe2002-08-27 09:48:53 +000034/* ------------------------------------------------------------------------- */
35
36/* Bus-to-Core Multiplier */
37#define _1x 2
38#define _1_5x 3
39#define _2x 4
40#define _2_5x 5
41#define _3x 6
42#define _3_5x 7
43#define _4x 8
44#define _4_5x 9
45#define _5x 10
46#define _5_5x 11
47#define _6x 12
48#define _6_5x 13
49#define _7x 14
50#define _7_5x 15
51#define _8x 16
52#define _byp -1
53#define _off -2
54#define _unk -3
55
56typedef struct {
57 int b2c_mult;
58 int vco_div;
59 char *freq_60x;
60 char *freq_core;
61} corecnf_t;
62
63/*
64 * this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
65 * Rev. 1, 8/2000, page 10.
66 */
67corecnf_t corecnf_tab[] = {
68 { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */
69 { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */
70 { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */
71 { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */
72 { _2x, 2, " 50-150", "100-300" }, /* 0x04 */
73 { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */
74 { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */
75 { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */
76 { _3x, 2, " 33-100", "100-300" }, /* 0x08 */
77 { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */
78 { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */
79 { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */
80 { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */
81 { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */
82 { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */
83 { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */
84 { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */
85 { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */
86 { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */
87 { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */
88 { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */
89 { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */
90 { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */
91 { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */
92 { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */
93 { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */
94 { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */
95 { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */
96 { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */
97 { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */
98 { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */
99 { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */
100};
101
102/* ------------------------------------------------------------------------- */
103
104/*
105 *
106 */
107
108int get_clocks (void)
109{
wdenk4a9cbbe2002-08-27 09:48:53 +0000110 volatile immap_t *immap = (immap_t *) CFG_IMMR;
111 ulong clkin;
112 ulong sccr, dfbrg;
113 ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
114 corecnf_t *cp;
115
116#if !defined(CONFIG_8260_CLKIN)
117#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
118#else
Heiko Schocherfa230442006-12-21 17:17:02 +0100119#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
120 clkin = board_get_cpu_clk_f ();
121#else
wdenk4a9cbbe2002-08-27 09:48:53 +0000122 clkin = CONFIG_8260_CLKIN;
123#endif
Heiko Schocherfa230442006-12-21 17:17:02 +0100124#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000125
126 sccr = immap->im_clkrst.car_sccr;
127 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
128
129 scmr = immap->im_clkrst.car_scmr;
130 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
wdenk4a9cbbe2002-08-27 09:48:53 +0000131 cp = &corecnf_tab[corecnf];
132
wdenk8564acf2003-07-14 22:13:32 +0000133 busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
134 cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
wdenk4a9cbbe2002-08-27 09:48:53 +0000135
wdenke1599e82004-10-10 23:27:33 +0000136 /* HiP7, HiP7 Rev01, HiP7 RevA */
137 if ((get_pvr () == PVR_8260_HIP7) ||
138 (get_pvr () == PVR_8260_HIP7R1) ||
139 (get_pvr () == PVR_8260_HIP7RA)) {
wdenk8564acf2003-07-14 22:13:32 +0000140 pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
141 gd->vco_out = clkin * (pllmf + 1);
142 } else { /* HiP3, HiP4 */
143 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
144 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
145 gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
146 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000147#if 0
148 if (gd->vco_out / (busdf + 1) != clkin) {
149 /* aaarrrggghhh!!! */
150 return (1);
151 }
152#endif
153
154 gd->cpm_clk = gd->vco_out / 2;
155 gd->bus_clk = clkin;
156 gd->scc_clk = gd->vco_out / 4;
157 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
158
159 if (cp->b2c_mult > 0) {
160 gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
161 } else {
162 gd->cpu_clk = clkin;
163 }
164
Stefan Roesef2302d42008-08-06 14:05:38 +0200165#ifdef CONFIG_PCI
166 gd->pci_clk = clkin;
167
168 if (sccr & SCCR_PCI_MODE) {
169 uint pci_div;
170 uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
171
172 if (sccr & SCCR_PCI_MODCK) {
173 pci_div = 2;
174 if (pcidf == 9) {
175 pci_div *= 5;
176 } else if (pcidf == 0xB) {
177 pci_div *= 6;
178 } else {
179 pci_div *= (pcidf + 1);
180 }
181 } else {
182 pci_div = pcidf + 1;
183 }
184
185 gd->pci_clk = (gd->cpm_clk * 2) / pci_div;
186 }
187#endif
188
wdenk4a9cbbe2002-08-27 09:48:53 +0000189 return (0);
190}
191
192int prt_8260_clks (void)
193{
wdenk4a9cbbe2002-08-27 09:48:53 +0000194 volatile immap_t *immap = (immap_t *) CFG_IMMR;
195 ulong sccr, dfbrg;
Wolfgang Denk23466d62006-03-12 16:14:29 +0100196 ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
wdenk4a9cbbe2002-08-27 09:48:53 +0000197 corecnf_t *cp;
198
199 sccr = immap->im_clkrst.car_sccr;
200 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
201
202 scmr = immap->im_clkrst.car_scmr;
203 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
204 busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
205 cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
206 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
207 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
Wolfgang Denk23466d62006-03-12 16:14:29 +0100208 pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
wdenk4a9cbbe2002-08-27 09:48:53 +0000209
210 cp = &corecnf_tab[corecnf];
211
wdenk4b9206e2004-03-23 22:14:11 +0000212 puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
wdenk4a9cbbe2002-08-27 09:48:53 +0000213
214 switch (cp->b2c_mult) {
215 case _byp:
wdenk4b9206e2004-03-23 22:14:11 +0000216 puts ("BYPASS");
wdenk4a9cbbe2002-08-27 09:48:53 +0000217 break;
218
219 case _off:
wdenk4b9206e2004-03-23 22:14:11 +0000220 puts ("OFF");
wdenk4a9cbbe2002-08-27 09:48:53 +0000221 break;
222
223 case _unk:
wdenk4b9206e2004-03-23 22:14:11 +0000224 puts ("UNKNOWN");
wdenk4a9cbbe2002-08-27 09:48:53 +0000225 break;
226
227 default:
228 printf ("%d%sx",
229 cp->b2c_mult / 2,
230 (cp->b2c_mult % 2) ? ".5" : "");
231 break;
232 }
233
234 printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
235 cp->vco_div, cp->freq_60x, cp->freq_core);
236
237 printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
Wolfgang Denk23466d62006-03-12 16:14:29 +0100238 "plldf %ld, pllmf %ld, pcidf %ld\n",
239 dfbrg, corecnf, busdf, cpmdf,
240 plldf, pllmf, pcidf);
wdenk4a9cbbe2002-08-27 09:48:53 +0000241
242 printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
243 gd->vco_out, gd->scc_clk, gd->brg_clk);
244
wdenk4b9206e2004-03-23 22:14:11 +0000245 printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
wdenk4a9cbbe2002-08-27 09:48:53 +0000246 gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
Stefan Roesef2302d42008-08-06 14:05:38 +0200247#ifdef CONFIG_PCI
248 printf (" - pci_clk %10ld\n", gd->pci_clk);
249#endif
wdenk4b9206e2004-03-23 22:14:11 +0000250 putc ('\n');
251
wdenk4a9cbbe2002-08-27 09:48:53 +0000252 return (0);
253}