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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Masahiro Yamada5f91a3a2015-02-10 21:37:01 +09002/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006
4 Free Software Foundation, Inc.
Masahiro Yamada5f91a3a2015-02-10 21:37:01 +09005 */
6
7!! libgcc routines for the Renesas / SuperH SH CPUs.
8!! Contributed by Steve Chamberlain.
9!! sac@cygnus.com
10
11!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
12!! recoded in assembly by Toshiyasu Morita
13!! tm@netcom.com
14
15/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
16 ELF local label prefixes by J"orn Rennecke
17 amylaar@cygnus.com */
18
19 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
20 /* n1 < d, but n1 might be larger than d1. */
21 .global __udiv_qrnnd_16
22 .balign 8
23__udiv_qrnnd_16:
24 div0u
25 cmp/hi r6,r0
26 bt .Lots
27 .rept 16
28 div1 r6,r0
29 .endr
30 extu.w r0,r1
31 bt 0f
32 add r6,r0
330: rotcl r1
34 mulu.w r1,r5
35 xtrct r4,r0
36 swap.w r0,r0
37 sts macl,r2
38 cmp/hs r2,r0
39 sub r2,r0
40 bt 0f
41 addc r5,r0
42 add #-1,r1
43 bt 0f
441: add #-1,r1
45 rts
46 add r5,r0
47 .balign 8
48.Lots:
49 sub r5,r0
50 swap.w r4,r1
51 xtrct r0,r1
52 clrt
53 mov r1,r0
54 addc r5,r0
55 mov #-1,r1
56 bf/s 1b
57 shlr16 r1
580: rts
59 nop