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wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050042#define CONFIG_CPM2 1 /* has CPM2 */
wdenk7abf0c52004-04-18 21:45:42 +000043#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
44
45#undef CONFIG_PCI /* pci ethernet support */
46#define CONFIG_TSEC_ENET /* tsec ethernet support*/
47#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
48#define CONFIG_ENV_OVERWRITE
49#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50#undef CONFIG_DDR_ECC /* only for ECC DDR module */
wdenk7abf0c52004-04-18 21:45:42 +000051#define CONFIG_DDR_DLL /* possible DLL fix needed */
wdenk9aea9532004-08-01 23:02:45 +000052#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk7abf0c52004-04-18 21:45:42 +000053
Kumar Gala572b13a2008-01-16 09:11:53 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk9aea9532004-08-01 23:02:45 +000055
56/* sysclk for MPC85xx
wdenk7abf0c52004-04-18 21:45:42 +000057 */
wdenk7abf0c52004-04-18 21:45:42 +000058
59#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
60
61/* Blinkin' LEDs for Robert :-)
62*/
63#define CONFIG_SHOW_ACTIVITY 1
64
wdenk9aea9532004-08-01 23:02:45 +000065/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
wdenk7abf0c52004-04-18 21:45:42 +000068#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk9aea9532004-08-01 23:02:45 +000069#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
wdenk7abf0c52004-04-18 21:45:42 +000071
wdenk9aea9532004-08-01 23:02:45 +000072#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk7abf0c52004-04-18 21:45:42 +000073
74#undef CFG_DRAM_TEST /* memory test, takes time */
75#define CFG_MEMTEST_START 0x00200000 /* memtest region */
76#define CFG_MEMTEST_END 0x00400000
77
wdenk7abf0c52004-04-18 21:45:42 +000078
79/* Localbus SDRAM is an option, not all boards have it.
wdenk9aea9532004-08-01 23:02:45 +000080 * This address, however, is used to configure a 256M local bus
81 * window that includes the Config latch below.
82 */
83#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
84#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk7abf0c52004-04-18 21:45:42 +000085
wdenk7abf0c52004-04-18 21:45:42 +000086#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
87#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk7abf0c52004-04-18 21:45:42 +000088
89#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
90#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
91#define CFG_MAX_FLASH_SECT 136 /* sectors per device */
92#undef CFG_FLASH_CHECKSUM
93#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
94#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
95
96/* The configuration latch is Chip Select 1.
wdenk9aea9532004-08-01 23:02:45 +000097 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk7abf0c52004-04-18 21:45:42 +000098 */
99#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */
100#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
101#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
102
103#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
104
105#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
106#define CFG_RAMBOOT
107#else
108#undef CFG_RAMBOOT
109#endif
110
111#ifdef CFG_RAMBOOT
112#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
113#else
114#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
115#endif
116#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -0600117#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenk7abf0c52004-04-18 21:45:42 +0000118#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
119
120
wdenk9aea9532004-08-01 23:02:45 +0000121/*
122 * DDR Setup
123 */
wdenk7abf0c52004-04-18 21:45:42 +0000124
wdenk9aea9532004-08-01 23:02:45 +0000125/*
126 * Base addresses -- Note these are effective addresses where the
127 * actual resources get mapped (not physical addresses)
128 */
129#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
130#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
131
132#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
wdenk7abf0c52004-04-18 21:45:42 +0000133
134#undef CONFIG_CLOCKS_IN_MHZ
135
136/* local bus definitions */
137#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
138#define CFG_OR2_PRELIM 0xfc006901
139#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
140#define CFG_LBC_LBCR 0x00000000
141#define CFG_LBC_LSRT 0x20000000
142#define CFG_LBC_MRTPR 0x20000000
143#define CFG_LBC_LSDMR_1 0x2861b723
144#define CFG_LBC_LSDMR_2 0x0861b723
145#define CFG_LBC_LSDMR_3 0x0861b723
146#define CFG_LBC_LSDMR_4 0x1861b723
147#define CFG_LBC_LSDMR_5 0x4061b723
148
149#define CONFIG_L1_INIT_RAM
150#define CFG_INIT_RAM_LOCK 1
151#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
152#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
153
154#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
155#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
156#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
157
158#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
159#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
160
161/* Serial Port */
162#define CONFIG_CONS_ON_SCC /* define if console on SCC */
163#undef CONFIG_CONS_NONE /* define if console on something else */
164#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
165
166#define CONFIG_BAUDRATE 38400
167
168#define CFG_BAUDRATE_TABLE \
169 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
170
171/* Use the HUSH parser */
172#define CFG_HUSH_PARSER
173#ifdef CFG_HUSH_PARSER
174#define CFG_PROMPT_HUSH_PS2 "> "
175#endif
176
Jon Loeliger20476722006-10-20 15:50:15 -0500177/*
178 * I2C
179 */
180#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
181#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk7abf0c52004-04-18 21:45:42 +0000182#undef CONFIG_SOFT_I2C /* I2C bit-banged */
183#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
184#define CFG_I2C_SLAVE 0x7F
185#if 0
186#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
187#else
188/* I did the 'if 0' so we could keep the syntax above if ever needed. */
189#undef CFG_I2C_NOPROBES
190#endif
Jon Loeliger20476722006-10-20 15:50:15 -0500191#define CFG_I2C_OFFSET 0x3000
wdenk7abf0c52004-04-18 21:45:42 +0000192
wdenk9aea9532004-08-01 23:02:45 +0000193/* RapdIO Map configuration, mapped 1:1.
194*/
195#define CFG_RIO_MEM_BASE 0xc0000000
196#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
197#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */
198
199/* Standard 8560 PCI addressing, mapped 1:1.
200*/
201#define CFG_PCI1_MEM_BASE 0x80000000
202#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
203#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
204#define CFG_PCI1_IO_BASE 0xe2000000
205#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
206#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk7abf0c52004-04-18 21:45:42 +0000207
208#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk9aea9532004-08-01 23:02:45 +0000209
wdenk7abf0c52004-04-18 21:45:42 +0000210#define CONFIG_NET_MULTI
wdenk7abf0c52004-04-18 21:45:42 +0000211#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk9aea9532004-08-01 23:02:45 +0000212
213#undef CONFIG_EEPRO100
214#undef CONFIG_TULIP
215
216#if !defined(CONFIG_PCI_PNP)
wdenk7abf0c52004-04-18 21:45:42 +0000217 #define PCI_ENET0_IOADDR 0xe0000000
218 #define PCI_ENET0_MEMADDR 0xe0000000
219 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk7abf0c52004-04-18 21:45:42 +0000220#endif
wdenk9aea9532004-08-01 23:02:45 +0000221
222#undef CONFIG_PCI_SCAN_SHOW
223#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
224
225#endif /* CONFIG_PCI */
226
227#if defined(CONFIG_TSEC_ENET)
228
229#ifndef CONFIG_NET_MULTI
wdenk7abf0c52004-04-18 21:45:42 +0000230#define CONFIG_NET_MULTI 1
wdenk9aea9532004-08-01 23:02:45 +0000231#endif
232
wdenk7abf0c52004-04-18 21:45:42 +0000233#define CONFIG_MII 1 /* MII PHY management */
wdenk9aea9532004-08-01 23:02:45 +0000234
Kim Phillips255a35772007-05-16 16:52:19 -0500235#define CONFIG_TSEC1 1
236#define CONFIG_TSEC1_NAME "TSEC0"
237#define CONFIG_TSEC2 1
238#define CONFIG_TSEC2_NAME "TSEC1"
wdenk9aea9532004-08-01 23:02:45 +0000239
240#define TSEC1_PHY_ADDR 2
241#define TSEC2_PHY_ADDR 4
242#define TSEC1_PHYIDX 0
243#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500244#define TSEC1_FLAGS TSEC_GIGABIT
245#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500246#define CONFIG_ETHPRIME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000247
wdenk7abf0c52004-04-18 21:45:42 +0000248#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk9aea9532004-08-01 23:02:45 +0000249
wdenk7abf0c52004-04-18 21:45:42 +0000250#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
251#undef CONFIG_ETHER_NONE /* define if ether on something else */
252#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk9aea9532004-08-01 23:02:45 +0000253
254#if (CONFIG_ETHER_INDEX == 2)
wdenk7abf0c52004-04-18 21:45:42 +0000255 /*
256 * - Rx-CLK is CLK13
257 * - Tx-CLK is CLK14
258 * - Select bus for bd/buffers
259 * - Full duplex
260 */
261 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
262 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
263 #define CFG_CPMFCR_RAMTYPE 0
264#if 0
265 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
266#else
267 #define CFG_FCC_PSMR 0
268#endif
269 #define FETH2_RST 0x01
wdenk9aea9532004-08-01 23:02:45 +0000270#elif (CONFIG_ETHER_INDEX == 3)
wdenk7abf0c52004-04-18 21:45:42 +0000271 /* need more definitions here for FE3 */
272 #define FETH3_RST 0x80
wdenk9aea9532004-08-01 23:02:45 +0000273#endif /* CONFIG_ETHER_INDEX */
274
275/* MDIO is done through the TSEC0 control.
276*/
wdenk7abf0c52004-04-18 21:45:42 +0000277#define CONFIG_MII /* MII PHY management */
278#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk7abf0c52004-04-18 21:45:42 +0000279
wdenk7abf0c52004-04-18 21:45:42 +0000280#endif
281
282/* Environment */
283/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk7abf0c52004-04-18 21:45:42 +0000284 */
285#ifndef CFG_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000286 #define CFG_ENV_IS_IN_FLASH 1
287 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
288 #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
wdenk7abf0c52004-04-18 21:45:42 +0000289 #define CFG_ENV_SIZE 0x2000
290#else
wdenk9aea9532004-08-01 23:02:45 +0000291 #define CFG_NO_FLASH 1 /* Flash is not usable now */
292 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
293 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
294 #define CFG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000295#endif
296
297#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk9aea9532004-08-01 23:02:45 +0000298#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk7abf0c52004-04-18 21:45:42 +0000299#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
300
301#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
302#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
303
Jon Loeliger2835e512007-06-13 13:22:08 -0500304/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500305 * BOOTP options
306 */
307#define CONFIG_BOOTP_BOOTFILESIZE
308#define CONFIG_BOOTP_BOOTPATH
309#define CONFIG_BOOTP_GATEWAY
310#define CONFIG_BOOTP_HOSTNAME
311
312
313/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500314 * Command line configuration.
315 */
316#include <config_cmd_default.h>
317
318#define CONFIG_CMD_PING
319#define CONFIG_CMD_I2C
320
wdenk9aea9532004-08-01 23:02:45 +0000321#if defined(CFG_RAMBOOT)
Jon Loeliger2835e512007-06-13 13:22:08 -0500322 #undef CONFIG_CMD_ENV
323 #undef CONFIG_CMD_LOADS
wdenk7abf0c52004-04-18 21:45:42 +0000324#else
Jon Loeliger2835e512007-06-13 13:22:08 -0500325 #define CONFIG_CMD_ELF
wdenk7abf0c52004-04-18 21:45:42 +0000326#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500327
328#if defined(CONFIG_PCI)
329 #define CONFIG_CMD_PCI
330#endif
331
332#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
333 #define CONFIG_CMD_MII
334#endif
335
wdenk7abf0c52004-04-18 21:45:42 +0000336
337#undef CONFIG_WATCHDOG /* watchdog disabled */
338
339/*
340 * Miscellaneous configurable options
341 */
342#define CFG_LONGHELP /* undef to save memory */
343#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500344#if defined(CONFIG_CMD_KGDB)
wdenk7abf0c52004-04-18 21:45:42 +0000345#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
346#else
347#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
348#endif
349#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
350#define CFG_MAXARGS 16 /* max number of command args */
351#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
352#define CFG_LOAD_ADDR 0x1000000 /* default load address */
353#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
354
355/*
356 * For booting Linux, the board info and command line data
357 * have to be in the first 8 MB of memory, since this is
358 * the maximum mapped by the Linux kernel during initialization.
359 */
360#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
361
wdenk7abf0c52004-04-18 21:45:42 +0000362/*
363 * Internal Definitions
364 *
365 * Boot Flags
366 */
367#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
368#define BOOTFLAG_WARM 0x02 /* Software reboot */
369
Jon Loeliger2835e512007-06-13 13:22:08 -0500370#if defined(CONFIG_CMD_KGDB)
wdenk7abf0c52004-04-18 21:45:42 +0000371#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
372#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
373#endif
374
375/*Note: change below for your network setting!!! */
376#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500377#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000378#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
379#define CONFIG_HAS_ETH1
wdenk9aea9532004-08-01 23:02:45 +0000380#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
wdenke2ffd592004-12-31 09:32:47 +0000381#define CONFIG_HAS_ETH2
wdenk9aea9532004-08-01 23:02:45 +0000382#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
wdenk7abf0c52004-04-18 21:45:42 +0000383#endif
384
385#define CONFIG_SERVERIP 192.168.85.1
386#define CONFIG_IPADDR 192.168.85.60
387#define CONFIG_GATEWAYIP 192.168.85.1
388#define CONFIG_NETMASK 255.255.255.0
389#define CONFIG_HOSTNAME STX_GP3
390#define CONFIG_ROOTPATH /gppproot
391#define CONFIG_BOOTFILE uImage
wdenk9aea9532004-08-01 23:02:45 +0000392#define CONFIG_LOADADDR 0x1000000
wdenk7abf0c52004-04-18 21:45:42 +0000393
394#endif /* __CONFIG_H */