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wdenkefa329c2004-03-23 20:18:25 +00001/*
2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkefa329c2004-03-23 20:18:25 +00006 */
7
8#include <common.h>
9#include <ioports.h>
10#include <mpc8260.h>
11#include <pci.h>
Ben Warren10efa022008-08-31 20:37:00 -070012#include <netdev.h>
wdenkefa329c2004-03-23 20:18:25 +000013
14/*
15 * I/O Port configuration table
16 *
17 * if conf is 1, then that port pin will be configured at boot time
18 * according to the five values podr/pdir/ppar/psor/pdat for that entry
19 */
20
21const iop_conf_t iop_conf_tab[4][32] = {
22
23 /* Port A configuration */
24 { /* conf ppar psor pdir podr pdat */
25 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
26 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
27 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
28 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
29 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
30 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
31 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
32 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
33 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
34 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
35 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
36 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
37 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
38 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
39 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
40 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
41 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
42 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
43 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
44 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
45 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
46 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
47 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
48 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
49 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
50 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
51 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
52 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
53 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
54 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
55 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
56 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
57 },
58
59 /* Port B configuration */
60 { /* conf ppar psor pdir podr pdat */
61 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
62 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
63 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
64#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
65#ifdef CONFIG_ETHER_ON_FCC2
66#error "SCC1 conflicts with FCC2"
67#endif
68 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
69#else
70 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
71#endif
72 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
73 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
74 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
75 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
76 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
77 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
78 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
79 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
80 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
81 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
82 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
83 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
84 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
85 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
86 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
87 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
88 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
89 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
90 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
91 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
92 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
93 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
94 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
95 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
96 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
97 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
98 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
99 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
100 },
101
102 /* Port C */
103 { /* conf ppar psor pdir podr pdat */
104 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
105 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
106 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
107 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
108 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
109 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
110 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
111 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
112 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
113 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
114 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
115 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
116 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
117 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
118 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
119 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
120 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
121 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
122 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
123 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
124 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
125 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
126 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
127 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
128 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
129 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
130 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
131 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
132 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
133 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
134 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
135 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
136 },
137
138 /* Port D */
139 { /* conf ppar psor pdir podr pdat */
140 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
141 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
142 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
143 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
144 /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
145 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
146 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
147 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
148 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
149 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
150 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
151 /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
152 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
153 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
154 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
155 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100156#if defined(CONFIG_SYS_I2C_SOFT)
wdenkefa329c2004-03-23 20:18:25 +0000157 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
158 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
159#else
160#if defined(CONFIG_HARD_I2C)
161 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
162 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
163#else /* normal I/O port pins */
164 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
165 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
166#endif
167#endif
168 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
169 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
170 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
171 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
172 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
173 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
174 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
175 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
176 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
177 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
178 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
181 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
182 }
183};
184
185/* ------------------------------------------------------------------------- */
186
187/* Check Board Identity:
188 */
189int checkboard (void)
190{
191 puts ("Board: PM828\n");
192 return 0;
193}
194
195/* ------------------------------------------------------------------------- */
196
197
198/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
199 *
200 * This routine performs standard 8260 initialization sequence
201 * and calculates the available memory size. It may be called
202 * several times to try different SDRAM configurations on both
203 * 60x and local buses.
204 */
205static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
206 ulong orx, volatile uchar * base)
207{
208 volatile uchar c = 0xff;
209 volatile ulong cnt, val;
210 volatile ulong *addr;
211 volatile uint *sdmr_ptr;
212 volatile uint *orx_ptr;
213 int i;
214 ulong save[32]; /* to make test non-destructive */
215 ulong maxsize;
216
217 /* We must be able to test a location outsize the maximum legal size
218 * to find out THAT we are outside; but this address still has to be
219 * mapped by the controller. That means, that the initial mapping has
220 * to be (at least) twice as large as the maximum expected size.
221 */
222 maxsize = (1 + (~orx | 0x7fff)) / 2;
223
224 sdmr_ptr = &memctl->memc_psdmr;
225 orx_ptr = &memctl->memc_or2;
226
227 *orx_ptr = orx;
228
229 /*
230 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
231 *
232 * "At system reset, initialization software must set up the
233 * programmable parameters in the memory controller banks registers
234 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
235 * system software should execute the following initialization sequence
236 * for each SDRAM device.
237 *
238 * 1. Issue a PRECHARGE-ALL-BANKS command
239 * 2. Issue eight CBR REFRESH commands
240 * 3. Issue a MODE-SET command to initialize the mode register
241 *
242 * The initial commands are executed by setting P/LSDMR[OP] and
243 * accessing the SDRAM with a single-byte transaction."
244 *
245 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkefa329c2004-03-23 20:18:25 +0000247 */
248
249 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
250 *base = c;
251
252 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
253 for (i = 0; i < 8; i++)
254 *base = c;
255
256 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
wdenkefa329c2004-03-23 20:18:25 +0000258
259 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
260 *base = c;
261
262 /*
263 * Check memory range for valid RAM. A simple memory test determines
264 * the actually available RAM size between addresses `base' and
265 * `base + maxsize'. Some (not all) hardware errors are detected:
266 * - short between address lines
267 * - short between data lines
268 */
269 i = 0;
270 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
271 addr = (volatile ulong *) base + cnt; /* pointer arith! */
272 save[i++] = *addr;
273 *addr = ~cnt;
274 }
275
276 addr = (volatile ulong *) base;
277 save[i] = *addr;
278 *addr = 0;
279
280 if ((val = *addr) != 0) {
281 *addr = save[i];
282 return (0);
283 }
284
285 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
286 addr = (volatile ulong *) base + cnt; /* pointer arith! */
287 val = *addr;
288 *addr = save[--i];
289 if (val != ~cnt) {
290 /* Write the actual size to ORx
291 */
292 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
293 return (cnt * sizeof (long));
294 }
295 }
296 return (maxsize);
297}
298
299
Becky Bruce9973e3c2008-06-09 16:03:40 -0500300phys_size_t initdram (int board_type)
wdenkefa329c2004-03-23 20:18:25 +0000301{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkefa329c2004-03-23 20:18:25 +0000303 volatile memctl8260_t *memctl = &immap->im_memctl;
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#ifndef CONFIG_SYS_RAMBOOT
wdenkefa329c2004-03-23 20:18:25 +0000306 ulong size8, size9;
307#endif
308 ulong psize = 32 * 1024 * 1024;
309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310 memctl->memc_psrt = CONFIG_SYS_PSRT;
311 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkefa329c2004-03-23 20:18:25 +0000312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#ifndef CONFIG_SYS_RAMBOOT
314 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
315 (uchar *) CONFIG_SYS_SDRAM_BASE);
316 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
317 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkefa329c2004-03-23 20:18:25 +0000318
319 if (size8 < size9) {
320 psize = size9;
321 printf ("(60x:9COL) ");
322 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
324 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkefa329c2004-03-23 20:18:25 +0000325 printf ("(60x:8COL) ");
326 }
327#endif
328 return (psize);
329}
330
Jon Loeliger3fe00102007-07-09 18:38:39 -0500331#if defined(CONFIG_CMD_DOC)
wdenkefa329c2004-03-23 20:18:25 +0000332void doc_init (void)
333{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334 doc_probe (CONFIG_SYS_DOC_BASE);
wdenkefa329c2004-03-23 20:18:25 +0000335}
336#endif
337
338#ifdef CONFIG_PCI
339struct pci_controller hose;
340
341extern void pci_mpc8250_init(struct pci_controller *);
342
343void pci_init_board(void)
344{
345 pci_mpc8250_init(&hose);
346}
347#endif
Ben Warren10efa022008-08-31 20:37:00 -0700348
349int board_eth_init(bd_t *bis)
350{
351 return pci_eth_init(bis);
352}