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Andy Fleming50586ef2008-10-30 16:47:16 -05001/*
2 * FSL SD/MMC Defines
3 *-------------------------------------------------------------------
4 *
Priyanka Jain32c8cfb2011-02-09 09:24:10 +05305 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
Andy Fleming50586ef2008-10-30 16:47:16 -05006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 *-------------------------------------------------------------------
23 *
24 */
25
26#ifndef __FSL_ESDHC_H__
27#define __FSL_ESDHC_H__
28
Anton Vorontsovb33433a2009-06-10 00:25:29 +040029#include <asm/errno.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010030#include <asm/byteorder.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040031
Andy Fleming50586ef2008-10-30 16:47:16 -050032/* FSL eSDHC-specific constants */
33#define SYSCTL 0x0002e02c
34#define SYSCTL_INITA 0x08000000
35#define SYSCTL_TIMEOUT_MASK 0x000f0000
Li Yang1118cdb2010-01-07 16:00:13 +080036#define SYSCTL_CLOCK_MASK 0x0000fff0
Stefano Babicc67bee12010-02-05 15:11:27 +010037#define SYSCTL_RSTA 0x01000000
38#define SYSCTL_CKEN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -050039#define SYSCTL_PEREN 0x00000004
40#define SYSCTL_HCKEN 0x00000002
41#define SYSCTL_IPGEN 0x00000001
Jerry Huang48bb3bb2010-03-18 15:57:06 -050042#define SYSCTL_RSTA 0x01000000
Andy Fleming50586ef2008-10-30 16:47:16 -050043
44#define IRQSTAT 0x0002e030
45#define IRQSTAT_DMAE (0x10000000)
46#define IRQSTAT_AC12E (0x01000000)
47#define IRQSTAT_DEBE (0x00400000)
48#define IRQSTAT_DCE (0x00200000)
49#define IRQSTAT_DTOE (0x00100000)
50#define IRQSTAT_CIE (0x00080000)
51#define IRQSTAT_CEBE (0x00040000)
52#define IRQSTAT_CCE (0x00020000)
53#define IRQSTAT_CTOE (0x00010000)
54#define IRQSTAT_CINT (0x00000100)
55#define IRQSTAT_CRM (0x00000080)
56#define IRQSTAT_CINS (0x00000040)
57#define IRQSTAT_BRR (0x00000020)
58#define IRQSTAT_BWR (0x00000010)
59#define IRQSTAT_DINT (0x00000008)
60#define IRQSTAT_BGE (0x00000004)
61#define IRQSTAT_TC (0x00000002)
62#define IRQSTAT_CC (0x00000001)
63
64#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
65#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
66
67#define IRQSTATEN 0x0002e034
68#define IRQSTATEN_DMAE (0x10000000)
69#define IRQSTATEN_AC12E (0x01000000)
70#define IRQSTATEN_DEBE (0x00400000)
71#define IRQSTATEN_DCE (0x00200000)
72#define IRQSTATEN_DTOE (0x00100000)
73#define IRQSTATEN_CIE (0x00080000)
74#define IRQSTATEN_CEBE (0x00040000)
75#define IRQSTATEN_CCE (0x00020000)
76#define IRQSTATEN_CTOE (0x00010000)
77#define IRQSTATEN_CINT (0x00000100)
78#define IRQSTATEN_CRM (0x00000080)
79#define IRQSTATEN_CINS (0x00000040)
80#define IRQSTATEN_BRR (0x00000020)
81#define IRQSTATEN_BWR (0x00000010)
82#define IRQSTATEN_DINT (0x00000008)
83#define IRQSTATEN_BGE (0x00000004)
84#define IRQSTATEN_TC (0x00000002)
85#define IRQSTATEN_CC (0x00000001)
86
87#define PRSSTAT 0x0002e024
88#define PRSSTAT_CLSL (0x00800000)
89#define PRSSTAT_WPSPL (0x00080000)
90#define PRSSTAT_CDPL (0x00040000)
91#define PRSSTAT_CINS (0x00010000)
92#define PRSSTAT_BREN (0x00000800)
Dipen Dudhat77c14582009-10-05 15:41:58 +053093#define PRSSTAT_BWEN (0x00000400)
Andy Fleming50586ef2008-10-30 16:47:16 -050094#define PRSSTAT_DLA (0x00000004)
95#define PRSSTAT_CICHB (0x00000002)
96#define PRSSTAT_CIDHB (0x00000001)
97
98#define PROCTL 0x0002e028
99#define PROCTL_INIT 0x00000020
100#define PROCTL_DTW_4 0x00000002
101#define PROCTL_DTW_8 0x00000004
102
103#define CMDARG 0x0002e008
104
105#define XFERTYP 0x0002e00c
106#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
107#define XFERTYP_CMDTYP_NORMAL 0x0
108#define XFERTYP_CMDTYP_SUSPEND 0x00400000
109#define XFERTYP_CMDTYP_RESUME 0x00800000
110#define XFERTYP_CMDTYP_ABORT 0x00c00000
111#define XFERTYP_DPSEL 0x00200000
112#define XFERTYP_CICEN 0x00100000
113#define XFERTYP_CCCEN 0x00080000
114#define XFERTYP_RSPTYP_NONE 0
115#define XFERTYP_RSPTYP_136 0x00010000
116#define XFERTYP_RSPTYP_48 0x00020000
117#define XFERTYP_RSPTYP_48_BUSY 0x00030000
118#define XFERTYP_MSBSEL 0x00000020
119#define XFERTYP_DTDSEL 0x00000010
120#define XFERTYP_AC12EN 0x00000004
121#define XFERTYP_BCEN 0x00000002
122#define XFERTYP_DMAEN 0x00000001
123
124#define CINS_TIMEOUT 1000
Dipen Dudhat77c14582009-10-05 15:41:58 +0530125#define PIO_TIMEOUT 100000
Andy Fleming50586ef2008-10-30 16:47:16 -0500126
127#define DSADDR 0x2e004
128
129#define CMDRSP0 0x2e010
130#define CMDRSP1 0x2e014
131#define CMDRSP2 0x2e018
132#define CMDRSP3 0x2e01c
133
134#define DATPORT 0x2e020
135
136#define WML 0x2e044
137#define WML_WRITE 0x00010000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530138#ifdef CONFIG_FSL_SDHC_V2_3
139#define WML_RD_WML_MAX 0x80
140#define WML_WR_WML_MAX 0x80
141#define WML_RD_WML_MAX_VAL 0x0
142#define WML_WR_WML_MAX_VAL 0x0
143#define WML_RD_WML_MASK 0x7f
144#define WML_WR_WML_MASK 0x7f0000
145#else
146#define WML_RD_WML_MAX 0x10
147#define WML_WR_WML_MAX 0x80
148#define WML_RD_WML_MAX_VAL 0x10
149#define WML_WR_WML_MAX_VAL 0x80
Roy Zangab467c52010-02-09 18:23:33 +0800150#define WML_RD_WML_MASK 0xff
151#define WML_WR_WML_MASK 0xff0000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530152#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500153
154#define BLKATTR 0x2e004
155#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
156#define BLKATTR_SIZE(x) (x & 0x1fff)
157#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
158
159#define ESDHC_HOSTCAPBLT_VS18 0x04000000
160#define ESDHC_HOSTCAPBLT_VS30 0x02000000
161#define ESDHC_HOSTCAPBLT_VS33 0x01000000
162#define ESDHC_HOSTCAPBLT_SRS 0x00800000
163#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
164#define ESDHC_HOSTCAPBLT_HSS 0x00200000
165
Stefano Babicc67bee12010-02-05 15:11:27 +0100166struct fsl_esdhc_cfg {
167 u32 esdhc_base;
168 u32 no_snoop;
Stefano Babicc67bee12010-02-05 15:11:27 +0100169};
170
171/* Select the correct accessors depending on endianess */
172#if __BYTE_ORDER == __LITTLE_ENDIAN
173#define esdhc_read32 in_le32
174#define esdhc_write32 out_le32
175#define esdhc_clrsetbits32 clrsetbits_le32
176#define esdhc_clrbits32 clrbits_le32
177#define esdhc_setbits32 setbits_le32
178#elif __BYTE_ORDER == __BIG_ENDIAN
179#define esdhc_read32 in_be32
180#define esdhc_write32 out_be32
181#define esdhc_clrsetbits32 clrsetbits_be32
182#define esdhc_clrbits32 clrbits_be32
183#define esdhc_setbits32 setbits_be32
184#else
185#error "Endianess is not defined: please fix to continue"
186#endif
187
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400188#ifdef CONFIG_FSL_ESDHC
Andy Fleming50586ef2008-10-30 16:47:16 -0500189int fsl_esdhc_mmc_init(bd_t *bis);
Stefano Babicc67bee12010-02-05 15:11:27 +0100190int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400191void fdt_fixup_esdhc(void *blob, bd_t *bd);
192#else
193static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
194static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
195#endif /* CONFIG_FSL_ESDHC */
Andy Fleming50586ef2008-10-30 16:47:16 -0500196
197#endif /* __FSL_ESDHC_H__ */