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Jason Liu18936ee2011-11-25 00:18:01 +00001/*
2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Jason Liu18936ee2011-11-25 00:18:01 +00008 */
9
Jeroen Hofstee5624c6b2014-10-08 22:57:52 +020010#include <bootm.h>
Jason Liu18936ee2011-11-25 00:18:01 +000011#include <common.h>
Jeroen Hofstee5624c6b2014-10-08 22:57:52 +020012#include <netdev.h>
Jason Liu18936ee2011-11-25 00:18:01 +000013#include <asm/errno.h>
14#include <asm/io.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/sys_proto.h>
Fabio Estevam6a376042012-04-29 08:11:13 +000018#include <asm/arch/crm_regs.h>
Tim Harvey70caa8e2015-05-18 06:56:46 -070019#include <imx_thermal.h>
Eric Nelsone1eb75b2012-09-23 07:30:55 +000020#include <ipu_pixfmt.h>
Ye.Li7a264162014-11-20 21:14:14 +080021#include <thermal.h>
Nikita Kiryanov44b98412014-11-21 12:47:26 +020022#include <sata.h>
Jason Liu18936ee2011-11-25 00:18:01 +000023
24#ifdef CONFIG_FSL_ESDHC
25#include <fsl_esdhc.h>
26#endif
27
Prabhakar Kushwaha28420e72015-05-18 17:13:52 +053028#if defined(CONFIG_DISPLAY_CPUINFO)
Eric Nelson11c2e502015-02-15 14:37:21 -070029static u32 reset_cause = -1;
30
31static char *get_reset_cause(void)
Jason Liu18936ee2011-11-25 00:18:01 +000032{
33 u32 cause;
34 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
35
36 cause = readl(&src_regs->srsr);
37 writel(cause, &src_regs->srsr);
Eric Nelson11c2e502015-02-15 14:37:21 -070038 reset_cause = cause;
Jason Liu18936ee2011-11-25 00:18:01 +000039
40 switch (cause) {
41 case 0x00001:
Fabio Estevamcece2622012-03-13 07:26:48 +000042 case 0x00011:
Jason Liu18936ee2011-11-25 00:18:01 +000043 return "POR";
44 case 0x00004:
45 return "CSU";
46 case 0x00008:
47 return "IPP USER";
48 case 0x00010:
Adrian Alonsocd562c82015-09-02 13:54:23 -050049#ifdef CONFIG_MX7
50 return "WDOG1";
51#else
Jason Liu18936ee2011-11-25 00:18:01 +000052 return "WDOG";
Adrian Alonsocd562c82015-09-02 13:54:23 -050053#endif
Jason Liu18936ee2011-11-25 00:18:01 +000054 case 0x00020:
55 return "JTAG HIGH-Z";
56 case 0x00040:
57 return "JTAG SW";
Adrian Alonsocd562c82015-09-02 13:54:23 -050058 case 0x00080:
59 return "WDOG3";
60#ifdef CONFIG_MX7
61 case 0x00100:
62 return "WDOG4";
63 case 0x00200:
64 return "TEMPSENSE";
65#else
66 case 0x00100:
67 return "TEMPSENSE";
Jason Liu18936ee2011-11-25 00:18:01 +000068 case 0x10000:
69 return "WARM BOOT";
Adrian Alonsocd562c82015-09-02 13:54:23 -050070#endif
Jason Liu18936ee2011-11-25 00:18:01 +000071 default:
72 return "unknown reset";
73 }
74}
75
Eric Nelson11c2e502015-02-15 14:37:21 -070076u32 get_imx_reset_cause(void)
77{
78 return reset_cause;
79}
Prabhakar Kushwaha28420e72015-05-18 17:13:52 +053080#endif
Eric Nelson11c2e502015-02-15 14:37:21 -070081
Troy Kiskyeb0344d2012-10-23 10:57:48 +000082#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
83#if defined(CONFIG_MX53)
Eric Nelson3e9cbbb2013-11-08 16:50:53 -070084#define MEMCTL_BASE ESDCTL_BASE_ADDR
Troy Kiskyeb0344d2012-10-23 10:57:48 +000085#else
Eric Nelson3e9cbbb2013-11-08 16:50:53 -070086#define MEMCTL_BASE MMDC_P0_BASE_ADDR
Troy Kiskyeb0344d2012-10-23 10:57:48 +000087#endif
88static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
89static const unsigned char bank_lookup[] = {3, 2};
90
Tim Harveyb07161c2014-06-02 16:13:21 -070091/* these MMDC registers are common to the IMX53 and IMX6 */
Troy Kiskyeb0344d2012-10-23 10:57:48 +000092struct esd_mmdc_regs {
93 uint32_t ctl;
94 uint32_t pdc;
95 uint32_t otc;
96 uint32_t cfg0;
97 uint32_t cfg1;
98 uint32_t cfg2;
99 uint32_t misc;
Troy Kiskyeb0344d2012-10-23 10:57:48 +0000100};
101
102#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
103#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
104#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
105#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
106#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
107
Tim Harveyb07161c2014-06-02 16:13:21 -0700108/*
109 * imx_ddr_size - return size in bytes of DRAM according MMDC config
110 * The MMDC MDCTL register holds the number of bits for row, col, and data
111 * width and the MMDC MDMISC register holds the number of banks. Combine
112 * all these bits to determine the meme size the MMDC has been configured for
113 */
Troy Kiskyeb0344d2012-10-23 10:57:48 +0000114unsigned imx_ddr_size(void)
115{
116 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
117 unsigned ctl = readl(&mem->ctl);
118 unsigned misc = readl(&mem->misc);
119 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
120
121 bits += ESD_MMDC_CTL_GET_ROW(ctl);
122 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
123 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
124 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
125 bits += ESD_MMDC_CTL_GET_CS1(ctl);
Marek Vasutfcfdfdd2014-08-04 01:47:09 +0200126
127 /* The MX6 can do only 3840 MiB of DRAM */
128 if (bits == 32)
129 return 0xf0000000;
130
Troy Kiskyeb0344d2012-10-23 10:57:48 +0000131 return 1 << bits;
132}
133#endif
134
Jason Liu18936ee2011-11-25 00:18:01 +0000135#if defined(CONFIG_DISPLAY_CPUINFO)
Fabio Estevama7683862012-03-20 04:21:45 +0000136
Troy Kisky20332a02012-10-23 10:57:46 +0000137const char *get_imx_type(u32 imxtype)
Fabio Estevama7683862012-03-20 04:21:45 +0000138{
139 switch (imxtype) {
Adrian Alonsocd562c82015-09-02 13:54:23 -0500140 case MXC_CPU_MX7D:
141 return "7D"; /* Dual-core version of the mx7 */
Peng Fand0acd992015-07-11 11:38:42 +0800142 case MXC_CPU_MX6QP:
143 return "6QP"; /* Quad-Plus version of the mx6 */
144 case MXC_CPU_MX6DP:
145 return "6DP"; /* Dual-Plus version of the mx6 */
Troy Kisky20332a02012-10-23 10:57:46 +0000146 case MXC_CPU_MX6Q:
Fabio Estevama7683862012-03-20 04:21:45 +0000147 return "6Q"; /* Quad-core version of the mx6 */
Fabio Estevam94db6652014-01-26 15:06:41 -0200148 case MXC_CPU_MX6D:
149 return "6D"; /* Dual-core version of the mx6 */
Troy Kisky20332a02012-10-23 10:57:46 +0000150 case MXC_CPU_MX6DL:
151 return "6DL"; /* Dual Lite version of the mx6 */
152 case MXC_CPU_MX6SOLO:
153 return "6SOLO"; /* Solo version of the mx6 */
154 case MXC_CPU_MX6SL:
Fabio Estevama7683862012-03-20 04:21:45 +0000155 return "6SL"; /* Solo-Lite version of the mx6 */
Fabio Estevam05d54b82014-06-24 17:40:58 -0300156 case MXC_CPU_MX6SX:
157 return "6SX"; /* SoloX version of the mx6 */
Peng Fan8631c062015-07-20 19:28:21 +0800158 case MXC_CPU_MX6UL:
159 return "6UL"; /* Ultra-Lite version of the mx6 */
Troy Kisky20332a02012-10-23 10:57:46 +0000160 case MXC_CPU_MX51:
Fabio Estevama7683862012-03-20 04:21:45 +0000161 return "51";
Troy Kisky20332a02012-10-23 10:57:46 +0000162 case MXC_CPU_MX53:
Fabio Estevama7683862012-03-20 04:21:45 +0000163 return "53";
164 default:
Otavio Salvadore972d722012-06-30 05:07:32 +0000165 return "??";
Fabio Estevama7683862012-03-20 04:21:45 +0000166 }
167}
168
Jason Liu18936ee2011-11-25 00:18:01 +0000169int print_cpuinfo(void)
170{
Stefano Babic943a3f22015-05-26 19:53:41 +0200171 u32 cpurev;
172 __maybe_unused u32 max_freq;
Jason Liu18936ee2011-11-25 00:18:01 +0000173
174 cpurev = get_cpu_rev();
Fabio Estevama7683862012-03-20 04:21:45 +0000175
Adrian Alonso1368f992015-09-02 13:54:13 -0500176#if defined(CONFIG_IMX_THERMAL)
177 struct udevice *thermal_dev;
178 int cpu_tmp, minc, maxc, ret;
179
Tim Harveyb83ddac2015-05-18 07:02:25 -0700180 printf("CPU: Freescale i.MX%s rev%d.%d",
181 get_imx_type((cpurev & 0xFF000) >> 12),
182 (cpurev & 0x000F0) >> 4,
183 (cpurev & 0x0000F) >> 0);
184 max_freq = get_cpu_speed_grade_hz();
185 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
186 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
187 } else {
188 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
189 mxc_get_clock(MXC_ARM_CLK) / 1000000);
190 }
191#else
Fabio Estevama7683862012-03-20 04:21:45 +0000192 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
193 get_imx_type((cpurev & 0xFF000) >> 12),
Jason Liu18936ee2011-11-25 00:18:01 +0000194 (cpurev & 0x000F0) >> 4,
195 (cpurev & 0x0000F) >> 0,
196 mxc_get_clock(MXC_ARM_CLK) / 1000000);
Tim Harveyb83ddac2015-05-18 07:02:25 -0700197#endif
Ye.Li7a264162014-11-20 21:14:14 +0800198
Adrian Alonso1368f992015-09-02 13:54:13 -0500199#if defined(CONFIG_IMX_THERMAL)
Tim Harvey70caa8e2015-05-18 06:56:46 -0700200 puts("CPU: ");
201 switch (get_cpu_temp_grade(&minc, &maxc)) {
202 case TEMP_AUTOMOTIVE:
203 puts("Automotive temperature grade ");
204 break;
205 case TEMP_INDUSTRIAL:
206 puts("Industrial temperature grade ");
207 break;
208 case TEMP_EXTCOMMERCIAL:
209 puts("Extended Commercial temperature grade ");
210 break;
211 default:
212 puts("Commercial temperature grade ");
213 break;
214 }
215 printf("(%dC to %dC)", minc, maxc);
Ye.Li7a264162014-11-20 21:14:14 +0800216 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
217 if (!ret) {
218 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
219
220 if (!ret)
Tim Harvey70caa8e2015-05-18 06:56:46 -0700221 printf(" at %dC\n", cpu_tmp);
Ye.Li7a264162014-11-20 21:14:14 +0800222 else
Fabio Estevam3a384b42015-09-08 14:43:10 -0300223 debug(" - invalid sensor data\n");
Ye.Li7a264162014-11-20 21:14:14 +0800224 } else {
Fabio Estevam3a384b42015-09-08 14:43:10 -0300225 debug(" - invalid sensor device\n");
Ye.Li7a264162014-11-20 21:14:14 +0800226 }
227#endif
228
Jason Liu18936ee2011-11-25 00:18:01 +0000229 printf("Reset cause: %s\n", get_reset_cause());
230 return 0;
231}
232#endif
233
234int cpu_eth_init(bd_t *bis)
235{
236 int rc = -ENODEV;
237
238#if defined(CONFIG_FEC_MXC)
239 rc = fecmxc_initialize(bis);
240#endif
241
242 return rc;
243}
244
Benoît Thébaudeauecb0f312012-08-17 10:42:55 +0000245#ifdef CONFIG_FSL_ESDHC
Jason Liu18936ee2011-11-25 00:18:01 +0000246/*
247 * Initializes on-chip MMC controllers.
248 * to override, implement board_mmc_init()
249 */
250int cpu_mmc_init(bd_t *bis)
251{
Jason Liu18936ee2011-11-25 00:18:01 +0000252 return fsl_esdhc_mmc_init(bis);
Jason Liu18936ee2011-11-25 00:18:01 +0000253}
Benoît Thébaudeauecb0f312012-08-17 10:42:55 +0000254#endif
Jason Liu18936ee2011-11-25 00:18:01 +0000255
Adrian Alonsocd562c82015-09-02 13:54:23 -0500256#ifndef CONFIG_MX7
Fabio Estevam6a376042012-04-29 08:11:13 +0000257u32 get_ahb_clk(void)
258{
259 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
260 u32 reg, ahb_podf;
261
262 reg = __raw_readl(&imx_ccm->cbcdr);
263 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
264 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
265
266 return get_periph_clk() / (ahb_podf + 1);
267}
Adrian Alonsocd562c82015-09-02 13:54:23 -0500268#endif
Eric Nelsone1eb75b2012-09-23 07:30:55 +0000269
Eric Nelsone1eb75b2012-09-23 07:30:55 +0000270void arch_preboot_os(void)
271{
Nikita Kiryanov44b98412014-11-21 12:47:26 +0200272#if defined(CONFIG_CMD_SATA)
273 sata_stop();
Soeren Mochdd1c8f12014-11-27 10:11:41 +0100274#if defined(CONFIG_MX6)
275 disable_sata_clock();
276#endif
Nikita Kiryanov44b98412014-11-21 12:47:26 +0200277#endif
278#if defined(CONFIG_VIDEO_IPUV3)
Eric Nelsone1eb75b2012-09-23 07:30:55 +0000279 /* disable video before launching O/S */
280 ipuv3_fb_shutdown();
Eric Nelsone1eb75b2012-09-23 07:30:55 +0000281#endif
Peng Fan623787f2015-10-29 15:54:51 +0800282#if defined(CONFIG_VIDEO_MXS)
283 lcdif_power_down();
284#endif
Nikita Kiryanov44b98412014-11-21 12:47:26 +0200285}
Fabio Estevam32c81ea2014-11-14 11:27:21 -0200286
287void set_chipselect_size(int const cs_size)
288{
289 unsigned int reg;
290 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
291 reg = readl(&iomuxc_regs->gpr[1]);
292
293 switch (cs_size) {
294 case CS0_128:
295 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
296 reg |= 0x5;
297 break;
298 case CS0_64M_CS1_64M:
299 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
300 reg |= 0x1B;
301 break;
302 case CS0_64M_CS1_32M_CS2_32M:
303 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
304 reg |= 0x4B;
305 break;
306 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
307 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
308 reg |= 0x249;
309 break;
310 default:
311 printf("Unknown chip select size: %d\n", cs_size);
312 break;
313 }
314
315 writel(reg, &iomuxc_regs->gpr[1]);
316}