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Asen Dimovb5d289f2010-04-20 22:49:04 +03001/*
2 * (C) Copyright 2010
3 * Ilko Iliev <iliev@ronetix.at>
4 * Asen Dimov <dimov@ronetix.at>
5 * Ronetix GmbH <www.ronetix.at>
6 *
7 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01008 * Stelian Pop <stelian@popies.net>
Asen Dimovb5d289f2010-04-20 22:49:04 +03009 * Lead Tech Design <www.leadtechdesign.com>
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Asen Dimovb5d289f2010-04-20 22:49:04 +030012 */
13
14#include <common.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040015#include <linux/sizes.h>
Asen Dimoveb6e6082011-06-08 22:01:37 +000016#include <asm/io.h>
Andreas Bießmannac45bb12013-11-29 12:13:45 +010017#include <asm/gpio.h>
Asen Dimovb5d289f2010-04-20 22:49:04 +030018#include <asm/arch/at91sam9_smc.h>
19#include <asm/arch/at91_common.h>
Asen Dimovb5d289f2010-04-20 22:49:04 +030020#include <asm/arch/at91_rstc.h>
21#include <asm/arch/at91_matrix.h>
Asen Dimoveb6e6082011-06-08 22:01:37 +000022#include <asm/arch/gpio.h>
Asen Dimovb5d289f2010-04-20 22:49:04 +030023#include <asm/arch/clk.h>
Asen Dimovb5d289f2010-04-20 22:49:04 +030024#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
25#include <net.h>
26#endif
27#include <netdev.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31/*
32 * Miscelaneous platform dependent initialisations
33 */
34
35#ifdef CONFIG_CMD_NAND
36static void pm9g45_nand_hw_init(void)
37{
38 unsigned long csa;
Asen Dimoveb6e6082011-06-08 22:01:37 +000039 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
Asen Dimovb5d289f2010-04-20 22:49:04 +030041
42 /* Enable CS3 */
43 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
44 writel(csa, &matrix->ccr[6]);
45
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
49 &smc->cs[3].setup);
50
51 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
53 &smc->cs[3].pulse);
54
55 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
56 &smc->cs[3].cycle);
57
58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 AT91_SMC_MODE_EXNW_DISABLE |
60 AT91_SMC_MODE_DBW_8 |
61 AT91_SMC_MODE_TDF_CYCLE(3),
62 &smc->cs[3].mode);
63
Wenyou Yang70341e22016-02-03 10:16:50 +080064 at91_periph_clk_enable(ATMEL_ID_PIOC);
Asen Dimovb5d289f2010-04-20 22:49:04 +030065
66#ifdef CONFIG_SYS_NAND_READY_PIN
67 /* Configure RDY/BSY */
Andreas Bießmannac45bb12013-11-29 12:13:45 +010068 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
Asen Dimovb5d289f2010-04-20 22:49:04 +030069#endif
70
71 /* Enable NandFlash */
Andreas Bießmannac45bb12013-11-29 12:13:45 +010072 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Asen Dimovb5d289f2010-04-20 22:49:04 +030073}
74#endif
75
76#ifdef CONFIG_MACB
77static void pm9g45_macb_hw_init(void)
78{
Asen Dimovb5d289f2010-04-20 22:49:04 +030079 /*
80 * PD2 enables the 50MHz oscillator for Ethernet PHY
81 * 1 - enable
82 * 0 - disable
83 */
84 at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
85 at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
86
Wenyou Yang70341e22016-02-03 10:16:50 +080087 at91_periph_clk_enable(ATMEL_ID_EMAC);
Asen Dimovb5d289f2010-04-20 22:49:04 +030088
89 /*
90 * Disable pull-up on:
91 * RXDV (PA15) => PHY normal mode (not Test mode)
92 * ERX0 (PA12) => PHY ADDR0
93 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
94 *
95 * PHY has internal pull-down
96 */
97 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
98 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
99 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
100
101 /* Re-enable pull-up */
102 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
103 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
104 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
105
106 at91_macb_hw_init();
107}
108#endif
109
Asen Dimovc4df2142011-12-09 11:00:07 +0000110int board_early_init_f(void)
Asen Dimovb5d289f2010-04-20 22:49:04 +0300111{
Wenyou Yang70341e22016-02-03 10:16:50 +0800112 at91_periph_clk_enable(ATMEL_ID_PIOA);
113 at91_periph_clk_enable(ATMEL_ID_PIOB);
114 at91_periph_clk_enable(ATMEL_ID_PIOC);
115 at91_periph_clk_enable(ATMEL_ID_PIODE);
Asen Dimovb5d289f2010-04-20 22:49:04 +0300116
Asen Dimovc4df2142011-12-09 11:00:07 +0000117 at91_seriald_hw_init();
118
119 return 0;
120}
121
122int board_init(void)
123{
124 /* arch number of AT91SAM9M10G45EK-Board */
125 gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
Asen Dimovb5d289f2010-04-20 22:49:04 +0300126 /* adress of boot parameters */
127 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
128
Asen Dimovb5d289f2010-04-20 22:49:04 +0300129#ifdef CONFIG_CMD_NAND
130 pm9g45_nand_hw_init();
131#endif
132
133#ifdef CONFIG_MACB
134 pm9g45_macb_hw_init();
135#endif
136 return 0;
137}
138
139int dram_init(void)
140{
Asen Dimov510f7942010-12-12 00:42:28 +0000141 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000142 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
Asen Dimov510f7942010-12-12 00:42:28 +0000143 PHYS_SDRAM_SIZE);
144 return 0;
145}
146
Simon Glass76b00ac2017-03-31 08:40:32 -0600147int dram_init_banksize(void)
Asen Dimov510f7942010-12-12 00:42:28 +0000148{
Asen Dimovb5d289f2010-04-20 22:49:04 +0300149 gd->bd->bi_dram[0].start = PHYS_SDRAM;
150 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
Simon Glass76b00ac2017-03-31 08:40:32 -0600151
152 return 0;
Asen Dimovb5d289f2010-04-20 22:49:04 +0300153}
154
155#ifdef CONFIG_RESET_PHY_R
156void reset_phy(void)
157{
158#ifdef CONFIG_MACB
159 /*
160 * Initialize ethernet HW addr prior to starting Linux,
161 * needed for nfsroot
162 */
Joe Hershbergerd2eaec62015-03-22 17:09:06 -0500163 eth_init();
Asen Dimovb5d289f2010-04-20 22:49:04 +0300164#endif
165}
166#endif
167
168int board_eth_init(bd_t *bis)
169{
170 int rc = 0;
171#ifdef CONFIG_MACB
Asen Dimoveb6e6082011-06-08 22:01:37 +0000172 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
Asen Dimovb5d289f2010-04-20 22:49:04 +0300173#endif
174 return rc;
175}