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Stefan Roeseb79316f2005-08-15 12:31:23 +02001/*
2 * Copyright (C) 2005 Sandburst Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
25 * Travis B. Sawyer
26 * Sandburst Corporation.
27 */
28#include <common.h>
29#include <ppc4xx.h>
30#if defined(CONFIG_440)
31# include <440_i2c.h>
32#else
33# include <405gp_i2c.h>
34#endif
35#include <i2c.h>
36#include <440_i2c.h>
37#include <command.h>
38#include "ppc440gx_i2c.h"
39
40#ifdef CONFIG_I2C_BUS1
41
Stefan Roeseb79316f2005-08-15 12:31:23 +020042#define IIC_OK 0
43#define IIC_NOK 1
44#define IIC_NOK_LA 2 /* Lost arbitration */
45#define IIC_NOK_ICT 3 /* Incomplete transfer */
46#define IIC_NOK_XFRA 4 /* Transfer aborted */
47#define IIC_NOK_DATA 5 /* No data in buffer */
48#define IIC_NOK_TOUT 6 /* Transfer timeout */
49
50#define IIC_TIMEOUT 1 /* 1 second */
51#if defined(CFG_I2C_NOPROBES)
52static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
53#endif
54
55static void _i2c_bus1_reset (void)
56{
57 int i, status;
58
59 /* Reset status register */
60 /* write 1 in SCMP and IRQA to clear these fields */
61 out8 (IIC_STS1, 0x0A);
62
63 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
64 out8 (IIC_EXTSTS1, 0x8F);
65 __asm__ volatile ("eieio");
66
67 /*
68 * Get current state, reset bus
69 * only if no transfers are pending.
70 */
71 i = 10;
72 do {
73 /* Get status */
74 status = in8 (IIC_STS1);
75 udelay (500); /* 500us */
76 i--;
77 } while ((status & IIC_STS_PT) && (i > 0));
78 /* Soft reset controller */
79 status = in8 (IIC_XTCNTLSS1);
80 out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
81 __asm__ volatile ("eieio");
82
83 /* make sure where in initial state, data hi, clock hi */
84 out8 (IIC_DIRECTCNTL1, 0xC);
85 for (i = 0; i < 10; i++) {
86 if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
87 /* clock until we get to known state */
88 out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
89 udelay (100); /* 100us */
90 out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
91 udelay (100); /* 100us */
92 } else {
93 break;
94 }
95 }
96 /* send start condition */
97 out8 (IIC_DIRECTCNTL1, 0x4);
98 udelay (1000); /* 1ms */
99 /* send stop condition */
100 out8 (IIC_DIRECTCNTL1, 0xC);
101 udelay (1000); /* 1ms */
102 /* Unreset controller */
103 out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
104 udelay (1000); /* 1ms */
105}
106
107void i2c1_init (int speed, int slaveadd)
108{
109 sys_info_t sysInfo;
110 unsigned long freqOPB;
111 int val, divisor;
112
113#ifdef CFG_I2C_INIT_BOARD
114 /* call board specific i2c bus reset routine before accessing the */
115 /* environment, which might be in a chip on that bus. For details */
116 /* about this problem see doc/I2C_Edge_Conditions. */
117 i2c_init_board();
118#endif
119
120 /* Handle possible failed I2C state */
121 /* FIXME: put this into i2c_init_board()? */
122 _i2c_bus1_reset ();
123
124 /* clear lo master address */
125 out8 (IIC_LMADR1, 0);
126
127 /* clear hi master address */
128 out8 (IIC_HMADR1, 0);
129
130 /* clear lo slave address */
131 out8 (IIC_LSADR1, 0);
132
133 /* clear hi slave address */
134 out8 (IIC_HSADR1, 0);
135
136 /* Clock divide Register */
137 /* get OPB frequency */
138 get_sys_info (&sysInfo);
139 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
140 /* set divisor according to freqOPB */
141 divisor = (freqOPB - 1) / 10000000;
142 if (divisor == 0)
143 divisor = 1;
144 out8 (IIC_CLKDIV1, divisor);
145
146 /* no interrupts */
147 out8 (IIC_INTRMSK1, 0);
148
149 /* clear transfer count */
150 out8 (IIC_XFRCNT1, 0);
151
152 /* clear extended control & stat */
153 /* write 1 in SRC SRS SWC SWS to clear these fields */
154 out8 (IIC_XTCNTLSS1, 0xF0);
155
156 /* Mode Control Register
157 Flush Slave/Master data buffer */
158 out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
159 __asm__ volatile ("eieio");
160
161
162 val = in8(IIC_MDCNTL1);
163 __asm__ volatile ("eieio");
164
165 /* Ignore General Call, slave transfers are ignored,
166 disable interrupts, exit unknown bus state, enable hold
167 SCL
168 100kHz normaly or FastMode for 400kHz and above
169 */
170
171 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
172 if( speed >= 400000 ){
173 val |= IIC_MDCNTL_FSM;
174 }
175 out8 (IIC_MDCNTL1, val);
176
177 /* clear control reg */
178 out8 (IIC_CNTL1, 0x00);
179 __asm__ volatile ("eieio");
180
181}
182
183/*
184 This code tries to use the features of the 405GP i2c
185 controller. It will transfer up to 4 bytes in one pass
186 on the loop. It only does out8(lbz) to the buffer when it
187 is possible to do out16(lhz) transfers.
188
189 cmd_type is 0 for write 1 for read.
190
191 addr_len can take any value from 0-255, it is only limited
192 by the char, we could make it larger if needed. If it is
193 0 we skip the address write cycle.
194
195 Typical case is a Write of an addr followd by a Read. The
196 IBM FAQ does not cover this. On the last byte of the write
197 we don't set the creg CHT bit, and on the first bytes of the
198 read we set the RPST bit.
199
200 It does not support address only transfers, there must be
201 a data part. If you want to write the address yourself, put
202 it in the data pointer.
203
204 It does not support transfer to/from address 0.
205
206 It does not check XFRCNT.
207*/
208static
209int i2c_transfer1(unsigned char cmd_type,
210 unsigned char chip,
211 unsigned char addr[],
212 unsigned char addr_len,
213 unsigned char data[],
214 unsigned short data_len )
215{
216 unsigned char* ptr;
217 int reading;
218 int tran,cnt;
219 int result;
220 int status;
221 int i;
222 uchar creg;
223
224 if( data == 0 || data_len == 0 ){
225 /*Don't support data transfer of no length or to address 0*/
226 printf( "i2c_transfer: bad call\n" );
227 return IIC_NOK;
228 }
229 if( addr && addr_len ){
230 ptr = addr;
231 cnt = addr_len;
232 reading = 0;
233 }else{
234 ptr = data;
235 cnt = data_len;
236 reading = cmd_type;
237 }
238
239 /*Clear Stop Complete Bit*/
240 out8(IIC_STS1,IIC_STS_SCMP);
241 /* Check init */
242 i=10;
243 do {
244 /* Get status */
245 status = in8(IIC_STS1);
246 __asm__ volatile("eieio");
247 i--;
248 } while ((status & IIC_STS_PT) && (i>0));
249
250 if (status & IIC_STS_PT) {
251 result = IIC_NOK_TOUT;
252 return(result);
253 }
254 /*flush the Master/Slave Databuffers*/
255 out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
256 /*need to wait 4 OPB clocks? code below should take that long*/
257
258 /* 7-bit adressing */
259 out8(IIC_HMADR1,0);
260 out8(IIC_LMADR1, chip);
261 __asm__ volatile("eieio");
262
263 tran = 0;
264 result = IIC_OK;
265 creg = 0;
266
267 while ( tran != cnt && (result == IIC_OK)) {
268 int bc,j;
269
270 /* Control register =
271 Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
272 Transfer is a sequence of transfers
273 */
274 creg |= IIC_CNTL_PT;
275
276 bc = (cnt - tran) > 4 ? 4 :
277 cnt - tran;
278 creg |= (bc-1)<<4;
279 /* if the real cmd type is write continue trans*/
280 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
281 creg |= IIC_CNTL_CHT;
282
283 if (reading)
284 creg |= IIC_CNTL_READ;
285 else {
286 for(j=0; j<bc; j++) {
287 /* Set buffer */
288 out8(IIC_MDBUF1,ptr[tran+j]);
289 __asm__ volatile("eieio");
290 }
291 }
292 out8(IIC_CNTL1, creg );
293 __asm__ volatile("eieio");
294
295 /* Transfer is in progress
296 we have to wait for upto 5 bytes of data
297 1 byte chip address+r/w bit then bc bytes
298 of data.
299 udelay(10) is 1 bit time at 100khz
300 Doubled for slop. 20 is too small.
301 */
302 i=2*5*8;
303 do {
304 /* Get status */
305 status = in8(IIC_STS1);
306 __asm__ volatile("eieio");
307 udelay (10);
308 i--;
309 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
310 && (i>0));
311
312 if (status & IIC_STS_ERR) {
313 result = IIC_NOK;
314 status = in8 (IIC_EXTSTS1);
315 /* Lost arbitration? */
316 if (status & IIC_EXTSTS_LA)
317 result = IIC_NOK_LA;
318 /* Incomplete transfer? */
319 if (status & IIC_EXTSTS_ICT)
320 result = IIC_NOK_ICT;
321 /* Transfer aborted? */
322 if (status & IIC_EXTSTS_XFRA)
323 result = IIC_NOK_XFRA;
324 } else if ( status & IIC_STS_PT) {
325 result = IIC_NOK_TOUT;
326 }
327 /* Command is reading => get buffer */
328 if ((reading) && (result == IIC_OK)) {
329 /* Are there data in buffer */
330 if (status & IIC_STS_MDBS) {
331 /*
332 even if we have data we have to wait 4OPB clocks
333 for it to hit the front of the FIFO, after that
334 we can just read. We should check XFCNT here and
335 if the FIFO is full there is no need to wait.
336 */
337 udelay (1);
338 for(j=0;j<bc;j++) {
339 ptr[tran+j] = in8(IIC_MDBUF1);
340 __asm__ volatile("eieio");
341 }
342 } else
343 result = IIC_NOK_DATA;
344 }
345 creg = 0;
346 tran+=bc;
347 if( ptr == addr && tran == cnt ) {
348 ptr = data;
349 cnt = data_len;
350 tran = 0;
351 reading = cmd_type;
352 if( reading )
353 creg = IIC_CNTL_RPST;
354 }
355 }
356 return (result);
357}
358
359int i2c_probe1 (uchar chip)
360{
361 uchar buf[1];
362
363 buf[0] = 0;
364
365 /*
366 * What is needed is to send the chip address and verify that the
367 * address was <ACK>ed (i.e. there was a chip at that address which
368 * drove the data line low).
369 */
370 return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
371}
372
373
374int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
375{
376 uchar xaddr[4];
377 int ret;
378
379 if ( alen > 4 ) {
380 printf ("I2C read: addr len %d not supported\n", alen);
381 return 1;
382 }
383
384 if ( alen > 0 ) {
385 xaddr[0] = (addr >> 24) & 0xFF;
386 xaddr[1] = (addr >> 16) & 0xFF;
387 xaddr[2] = (addr >> 8) & 0xFF;
388 xaddr[3] = addr & 0xFF;
389 }
390
391
392#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
393 /*
394 * EEPROM chips that implement "address overflow" are ones
395 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
396 * address and the extra bits end up in the "chip address"
397 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
398 * four 256 byte chips.
399 *
400 * Note that we consider the length of the address field to
401 * still be one byte because the extra address bits are
402 * hidden in the chip address.
403 */
404 if( alen > 0 )
405 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
406#endif
407 if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
408 printf( "I2c read: failed %d\n", ret);
409 return 1;
410 }
411 return 0;
412}
413
414int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
415{
416 uchar xaddr[4];
417
418 if ( alen > 4 ) {
419 printf ("I2C write: addr len %d not supported\n", alen);
420 return 1;
421
422 }
423 if ( alen > 0 ) {
424 xaddr[0] = (addr >> 24) & 0xFF;
425 xaddr[1] = (addr >> 16) & 0xFF;
426 xaddr[2] = (addr >> 8) & 0xFF;
427 xaddr[3] = addr & 0xFF;
428 }
429
430#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
431 /*
432 * EEPROM chips that implement "address overflow" are ones
433 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
434 * address and the extra bits end up in the "chip address"
435 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
436 * four 256 byte chips.
437 *
438 * Note that we consider the length of the address field to
439 * still be one byte because the extra address bits are
440 * hidden in the chip address.
441 */
442 if( alen > 0 )
443 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
444#endif
445
446 return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
447}
448
449/*-----------------------------------------------------------------------
450 * Read a register
451 */
452uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
453{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200454 uchar buf;
Stefan Roeseb79316f2005-08-15 12:31:23 +0200455
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200456 i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200457
458 return(buf);
459}
460
461/*-----------------------------------------------------------------------
462 * Write a register
463 */
464void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
465{
466 i2c_write1(i2c_addr, reg, 1, &val, 1);
467}
468
469
470int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
471{
472 int j;
473#if defined(CFG_I2C_NOPROBES)
474 int k, skip;
475#endif
476
477 puts ("Valid chip addresses:");
478 for(j = 0; j < 128; j++) {
479#if defined(CFG_I2C_NOPROBES)
480 skip = 0;
481 for (k = 0; k < sizeof(i2c_no_probes); k++){
482 if (j == i2c_no_probes[k]){
483 skip = 1;
484 break;
485 }
486 }
487 if (skip)
488 continue;
489#endif
490 if(i2c_probe1(j) == 0) {
491 printf(" %02X", j);
492 }
493 }
494 putc ('\n');
495
496#if defined(CFG_I2C_NOPROBES)
497 puts ("Excluded chip addresses:");
498 for( k = 0; k < sizeof(i2c_no_probes); k++ )
499 printf(" %02X", i2c_no_probes[k] );
500 putc ('\n');
501#endif
502
503 return 0;
504}
505
506U_BOOT_CMD(
507 iprobe1, 1, 1, do_i2c1_probe,
508 "iprobe1 - probe to discover valid I2C chip addresses\n",
509 "\n -discover valid I2C chip addresses\n"
510);
511
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200512#endif /* CONFIG_I2C_BUS1 */