Bhupesh Sharma | 2e5c2fe | 2023-04-04 02:01:20 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> |
| 4 | * |
| 5 | * Based on Linux driver |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <generic-phy.h> |
| 11 | #include <linux/bitops.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <reset.h> |
| 14 | #include <clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | |
| 17 | #include <dt-bindings/phy/phy-qcom-qusb2.h> |
| 18 | |
| 19 | #define QUSB2PHY_PLL 0x0 |
| 20 | #define QUSB2PHY_PLL_TEST 0x04 |
| 21 | #define CLK_REF_SEL BIT(7) |
| 22 | |
| 23 | #define QUSB2PHY_PLL_TUNE 0x08 |
| 24 | #define QUSB2PHY_PLL_USER_CTL1 0x0c |
| 25 | #define QUSB2PHY_PLL_USER_CTL2 0x10 |
| 26 | #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c |
| 27 | #define QUSB2PHY_PLL_PWR_CTRL 0x18 |
| 28 | |
| 29 | /* QUSB2PHY_PLL_STATUS register bits */ |
| 30 | #define PLL_LOCKED BIT(5) |
| 31 | |
| 32 | /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ |
| 33 | #define CORE_READY_STATUS BIT(0) |
| 34 | |
| 35 | /* QUSB2PHY_PORT_POWERDOWN register bits */ |
| 36 | #define CLAMP_N_EN BIT(5) |
| 37 | #define FREEZIO_N BIT(1) |
| 38 | #define POWER_DOWN BIT(0) |
| 39 | |
| 40 | /* QUSB2PHY_PWR_CTRL1 register bits */ |
| 41 | #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) |
| 42 | #define PWR_CTRL1_CLAMP_N_EN BIT(1) |
| 43 | |
| 44 | #define QUSB2PHY_REFCLK_ENABLE BIT(0) |
| 45 | |
| 46 | #define PHY_CLK_SCHEME_SEL BIT(0) |
| 47 | |
| 48 | /* QUSB2PHY_INTR_CTRL register bits */ |
| 49 | #define DMSE_INTR_HIGH_SEL BIT(4) |
| 50 | #define DPSE_INTR_HIGH_SEL BIT(3) |
| 51 | #define CHG_DET_INTR_EN BIT(2) |
| 52 | #define DMSE_INTR_EN BIT(1) |
| 53 | #define DPSE_INTR_EN BIT(0) |
| 54 | |
| 55 | /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ |
| 56 | #define CORE_PLL_EN_FROM_RESET BIT(4) |
| 57 | #define CORE_RESET BIT(5) |
| 58 | #define CORE_RESET_MUX BIT(6) |
| 59 | |
| 60 | /* QUSB2PHY_IMP_CTRL1 register bits */ |
| 61 | #define IMP_RES_OFFSET_MASK GENMASK(5, 0) |
| 62 | #define IMP_RES_OFFSET_SHIFT 0x0 |
| 63 | |
| 64 | /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ |
| 65 | #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) |
| 66 | #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 |
| 67 | |
| 68 | /* QUSB2PHY_CHG_CONTROL_2 register bits */ |
| 69 | #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) |
| 70 | #define CHG_CTRL2_OFFSET_SHIFT 0x4 |
| 71 | |
| 72 | /* QUSB2PHY_PORT_TUNE1 register bits */ |
| 73 | #define HSTX_TRIM_MASK GENMASK(7, 4) |
| 74 | #define HSTX_TRIM_SHIFT 0x4 |
| 75 | #define PREEMPH_WIDTH_HALF_BIT BIT(2) |
| 76 | #define PREEMPHASIS_EN_MASK GENMASK(1, 0) |
| 77 | #define PREEMPHASIS_EN_SHIFT 0x0 |
| 78 | |
| 79 | /* QUSB2PHY_PORT_TUNE2 register bits */ |
| 80 | #define HSDISC_TRIM_MASK GENMASK(1, 0) |
| 81 | #define HSDISC_TRIM_SHIFT 0x0 |
| 82 | |
| 83 | #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 |
| 84 | #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c |
| 85 | #define QUSB2PHY_PLL_CMODE 0x2c |
| 86 | #define QUSB2PHY_PLL_LOCK_DELAY 0x184 |
| 87 | #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 |
| 88 | #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 |
| 89 | #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 |
| 90 | #define QUSB2PHY_PWR_CTRL2 0x214 |
| 91 | #define QUSB2PHY_IMP_CTRL1 0x220 |
| 92 | #define QUSB2PHY_IMP_CTRL2 0x224 |
| 93 | #define QUSB2PHY_CHG_CTRL2 0x23c |
| 94 | |
| 95 | struct qusb2_phy_init_tbl { |
| 96 | unsigned int offset; |
| 97 | unsigned int val; |
| 98 | /* |
| 99 | * register part of layout ? |
| 100 | * if yes, then offset gives index in the reg-layout |
| 101 | */ |
| 102 | int in_layout; |
| 103 | }; |
| 104 | |
| 105 | struct qusb2_phy_cfg { |
| 106 | const struct qusb2_phy_init_tbl *tbl; |
| 107 | /* number of entries in the table */ |
| 108 | unsigned int tbl_num; |
| 109 | /* offset to PHY_CLK_SCHEME register in TCSR map */ |
| 110 | unsigned int clk_scheme_offset; |
| 111 | |
| 112 | /* array of registers with different offsets */ |
| 113 | const unsigned int *regs; |
| 114 | unsigned int mask_core_ready; |
| 115 | unsigned int disable_ctrl; |
| 116 | unsigned int autoresume_en; |
| 117 | |
| 118 | /* true if PHY has PLL_TEST register to select clk_scheme */ |
| 119 | bool has_pll_test; |
| 120 | |
| 121 | /* true if TUNE1 register must be updated by fused value, else TUNE2 */ |
| 122 | bool update_tune1_with_efuse; |
| 123 | |
| 124 | /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ |
| 125 | bool has_pll_override; |
| 126 | }; |
| 127 | |
| 128 | /* set of registers with offsets different per-PHY */ |
| 129 | enum qusb2phy_reg_layout { |
| 130 | QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, |
| 131 | QUSB2PHY_PLL_STATUS, |
| 132 | QUSB2PHY_PORT_TUNE1, |
| 133 | QUSB2PHY_PORT_TUNE2, |
| 134 | QUSB2PHY_PORT_TUNE3, |
| 135 | QUSB2PHY_PORT_TUNE4, |
| 136 | QUSB2PHY_PORT_TUNE5, |
| 137 | QUSB2PHY_PORT_TEST1, |
| 138 | QUSB2PHY_PORT_TEST2, |
| 139 | QUSB2PHY_PORT_POWERDOWN, |
| 140 | QUSB2PHY_INTR_CTRL, |
| 141 | }; |
| 142 | |
| 143 | #define QUSB2_PHY_INIT_CFG(o, v) \ |
| 144 | { \ |
| 145 | .offset = o, \ |
| 146 | .val = v, \ |
| 147 | } |
| 148 | |
| 149 | #define QUSB2_PHY_INIT_CFG_L(o, v) \ |
| 150 | { \ |
| 151 | .offset = o, \ |
| 152 | .val = v, \ |
| 153 | .in_layout = 1, \ |
| 154 | } |
| 155 | |
| 156 | static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { |
| 157 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), |
| 158 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), |
| 159 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), |
| 160 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), |
| 161 | |
| 162 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), |
| 163 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), |
| 164 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), |
| 165 | |
| 166 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), |
| 167 | |
| 168 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), |
| 169 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), |
| 170 | }; |
| 171 | |
| 172 | static const unsigned int sm6115_regs_layout[] = { |
| 173 | [QUSB2PHY_PLL_STATUS] = 0x38, |
| 174 | [QUSB2PHY_PORT_TUNE1] = 0x80, |
| 175 | [QUSB2PHY_PORT_TUNE2] = 0x84, |
| 176 | [QUSB2PHY_PORT_TUNE3] = 0x88, |
| 177 | [QUSB2PHY_PORT_TUNE4] = 0x8c, |
| 178 | [QUSB2PHY_PORT_TUNE5] = 0x90, |
| 179 | [QUSB2PHY_PORT_TEST1] = 0xb8, |
| 180 | [QUSB2PHY_PORT_TEST2] = 0x9c, |
| 181 | [QUSB2PHY_PORT_POWERDOWN] = 0xb4, |
| 182 | [QUSB2PHY_INTR_CTRL] = 0xbc, |
| 183 | }; |
| 184 | |
Caleb Connolly | 78fdfd9 | 2023-09-04 15:54:10 +0100 | [diff] [blame^] | 185 | static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { |
| 186 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), |
| 187 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), |
| 188 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), |
| 189 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), |
| 190 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), |
| 191 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), |
| 192 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), |
| 193 | QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), |
| 194 | QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), |
| 195 | QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), |
| 196 | |
| 197 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), |
| 198 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), |
| 199 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), |
| 200 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), |
| 201 | QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), |
| 202 | |
| 203 | QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), |
| 204 | }; |
| 205 | |
| 206 | static const unsigned int qusb2_v2_regs_layout[] = { |
| 207 | [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, |
| 208 | [QUSB2PHY_PLL_STATUS] = 0x1a0, |
| 209 | [QUSB2PHY_PORT_TUNE1] = 0x240, |
| 210 | [QUSB2PHY_PORT_TUNE2] = 0x244, |
| 211 | [QUSB2PHY_PORT_TUNE3] = 0x248, |
| 212 | [QUSB2PHY_PORT_TUNE4] = 0x24c, |
| 213 | [QUSB2PHY_PORT_TUNE5] = 0x250, |
| 214 | [QUSB2PHY_PORT_TEST1] = 0x254, |
| 215 | [QUSB2PHY_PORT_TEST2] = 0x258, |
| 216 | [QUSB2PHY_PORT_POWERDOWN] = 0x210, |
| 217 | [QUSB2PHY_INTR_CTRL] = 0x230, |
| 218 | }; |
| 219 | |
Bhupesh Sharma | 2e5c2fe | 2023-04-04 02:01:20 +0530 | [diff] [blame] | 220 | static const struct qusb2_phy_cfg sm6115_phy_cfg = { |
| 221 | .tbl = sm6115_init_tbl, |
| 222 | .tbl_num = ARRAY_SIZE(sm6115_init_tbl), |
| 223 | .regs = sm6115_regs_layout, |
| 224 | |
| 225 | .has_pll_test = true, |
| 226 | .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), |
| 227 | .mask_core_ready = PLL_LOCKED, |
| 228 | .autoresume_en = BIT(3), |
| 229 | }; |
| 230 | |
Caleb Connolly | 78fdfd9 | 2023-09-04 15:54:10 +0100 | [diff] [blame^] | 231 | static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { |
| 232 | .tbl = qusb2_v2_init_tbl, |
| 233 | .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), |
| 234 | .regs = qusb2_v2_regs_layout, |
| 235 | |
| 236 | .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | |
| 237 | POWER_DOWN), |
| 238 | .mask_core_ready = CORE_READY_STATUS, |
| 239 | .has_pll_override = true, |
| 240 | .autoresume_en = BIT(0), |
| 241 | .update_tune1_with_efuse = true, |
| 242 | }; |
| 243 | |
Bhupesh Sharma | 2e5c2fe | 2023-04-04 02:01:20 +0530 | [diff] [blame] | 244 | /** |
| 245 | * struct qusb2_phy - structure holding qusb2 phy attributes |
| 246 | * |
| 247 | * @phy: generic phy |
| 248 | * @base: iomapped memory space for qubs2 phy |
| 249 | * |
| 250 | * @cfg_ahb_clk: AHB2PHY interface clock |
| 251 | * @ref_clk: phy reference clock |
| 252 | * @iface_clk: phy interface clock |
| 253 | * @phy_rst: phy reset control |
| 254 | * |
| 255 | * @cfg: phy config data |
| 256 | * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme |
| 257 | */ |
| 258 | struct qusb2_phy { |
| 259 | struct phy *phy; |
| 260 | void __iomem *base; |
| 261 | |
| 262 | struct clk *cfg_ahb_clk; |
| 263 | struct clk *ref_clk; |
| 264 | struct clk *iface_clk; |
| 265 | struct clk_bulk clks; |
| 266 | struct reset_ctl phy_rst; |
| 267 | |
| 268 | const struct qusb2_phy_cfg *cfg; |
| 269 | bool has_se_clk_scheme; |
| 270 | }; |
| 271 | |
| 272 | static inline void qusb2_write_mask(void __iomem *base, u32 offset, |
| 273 | u32 val, u32 mask) |
| 274 | { |
| 275 | u32 reg; |
| 276 | |
| 277 | reg = readl(base + offset); |
| 278 | reg &= ~mask; |
| 279 | reg |= val & mask; |
| 280 | writel(reg, base + offset); |
| 281 | |
| 282 | /* Ensure above write is completed */ |
| 283 | readl(base + offset); |
| 284 | } |
| 285 | |
| 286 | static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) |
| 287 | { |
| 288 | u32 reg; |
| 289 | |
| 290 | reg = readl(base + offset); |
| 291 | reg |= val; |
| 292 | writel(reg, base + offset); |
| 293 | |
| 294 | /* Ensure above write is completed */ |
| 295 | readl(base + offset); |
| 296 | } |
| 297 | |
| 298 | static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) |
| 299 | { |
| 300 | u32 reg; |
| 301 | |
| 302 | reg = readl(base + offset); |
| 303 | reg &= ~val; |
| 304 | writel(reg, base + offset); |
| 305 | |
| 306 | /* Ensure above write is completed */ |
| 307 | readl(base + offset); |
| 308 | } |
| 309 | |
| 310 | static inline |
| 311 | void qusb2_phy_configure(void __iomem *base, |
| 312 | const unsigned int *regs, |
| 313 | const struct qusb2_phy_init_tbl tbl[], int num) |
| 314 | { |
| 315 | int i; |
| 316 | |
| 317 | for (i = 0; i < num; i++) { |
| 318 | if (tbl[i].in_layout) |
| 319 | writel(tbl[i].val, base + regs[tbl[i].offset]); |
| 320 | else |
| 321 | writel(tbl[i].val, base + tbl[i].offset); |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static int qusb2phy_do_reset(struct qusb2_phy *qphy) |
| 326 | { |
| 327 | int ret; |
| 328 | |
| 329 | ret = reset_assert(&qphy->phy_rst); |
| 330 | if (ret) |
| 331 | return ret; |
| 332 | |
| 333 | udelay(10); |
| 334 | |
| 335 | ret = reset_deassert(&qphy->phy_rst); |
| 336 | if (ret) |
| 337 | return ret; |
| 338 | |
| 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | static int qusb2phy_power_on(struct phy *phy) |
| 343 | { |
| 344 | struct qusb2_phy *qphy = dev_get_priv(phy->dev); |
| 345 | const struct qusb2_phy_cfg *cfg = qphy->cfg; |
| 346 | int ret; |
| 347 | u32 val; |
| 348 | |
| 349 | ret = qusb2phy_do_reset(qphy); |
| 350 | if (ret) |
| 351 | return ret; |
| 352 | |
| 353 | /* Disable the PHY */ |
| 354 | qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], |
| 355 | qphy->cfg->disable_ctrl); |
| 356 | |
| 357 | if (cfg->has_pll_test) { |
| 358 | /* save reset value to override reference clock scheme later */ |
| 359 | val = readl(qphy->base + QUSB2PHY_PLL_TEST); |
| 360 | } |
| 361 | |
| 362 | qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, |
| 363 | cfg->tbl_num); |
| 364 | |
| 365 | /* Enable the PHY */ |
| 366 | qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], |
| 367 | POWER_DOWN); |
| 368 | |
| 369 | /* Required to get phy pll lock successfully */ |
| 370 | udelay(150); |
| 371 | |
| 372 | if (cfg->has_pll_test) { |
| 373 | val |= CLK_REF_SEL; |
| 374 | |
| 375 | writel(val, qphy->base + QUSB2PHY_PLL_TEST); |
| 376 | |
| 377 | /* ensure above write is through */ |
| 378 | readl(qphy->base + QUSB2PHY_PLL_TEST); |
| 379 | } |
| 380 | |
| 381 | /* Required to get phy pll lock successfully */ |
| 382 | udelay(100); |
| 383 | |
| 384 | val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); |
| 385 | if (!(val & cfg->mask_core_ready)) { |
| 386 | pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val); |
| 387 | ret = -EBUSY; |
| 388 | return ret; |
| 389 | } |
| 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int qusb2phy_power_off(struct phy *phy) |
| 395 | { |
| 396 | struct qusb2_phy *qphy = dev_get_priv(phy->dev); |
| 397 | |
| 398 | /* Disable the PHY */ |
| 399 | qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], |
| 400 | qphy->cfg->disable_ctrl); |
| 401 | |
| 402 | reset_assert(&qphy->phy_rst); |
| 403 | |
| 404 | clk_disable_bulk(&qphy->clks); |
| 405 | clk_release_bulk(&qphy->clks); |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy) |
| 411 | { |
| 412 | int ret; |
| 413 | |
| 414 | ret = clk_get_bulk(dev, &qphy->clks); |
| 415 | if (ret == -ENOSYS || ret == -ENOENT) |
| 416 | return 0; |
| 417 | if (ret) |
| 418 | return ret; |
| 419 | |
| 420 | ret = clk_enable_bulk(&qphy->clks); |
| 421 | if (ret) { |
| 422 | clk_release_bulk(&qphy->clks); |
| 423 | return ret; |
| 424 | } |
| 425 | |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | static int qusb2phy_probe(struct udevice *dev) |
| 430 | { |
| 431 | struct qusb2_phy *qphy = dev_get_priv(dev); |
| 432 | int ret; |
| 433 | |
| 434 | qphy->base = (void __iomem *)dev_read_addr(dev); |
| 435 | if (IS_ERR(qphy->base)) |
| 436 | return PTR_ERR(qphy->base); |
| 437 | |
| 438 | ret = qusb2phy_clk_init(dev, qphy); |
| 439 | if (ret) |
| 440 | return ret; |
| 441 | |
Caleb Connolly | 78fdfd9 | 2023-09-04 15:54:10 +0100 | [diff] [blame^] | 442 | ret = reset_get_by_index(dev, 0, &qphy->phy_rst); |
Bhupesh Sharma | 2e5c2fe | 2023-04-04 02:01:20 +0530 | [diff] [blame] | 443 | if (ret) |
| 444 | return ret; |
| 445 | |
| 446 | qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev); |
| 447 | if (!qphy->cfg) |
| 448 | return -EINVAL; |
| 449 | |
| 450 | return 0; |
| 451 | } |
| 452 | |
| 453 | static struct phy_ops qusb2phy_ops = { |
| 454 | .power_on = qusb2phy_power_on, |
| 455 | .power_off = qusb2phy_power_off, |
| 456 | }; |
| 457 | |
| 458 | static const struct udevice_id qusb2phy_ids[] = { |
| 459 | { .compatible = "qcom,qusb2-phy" }, |
| 460 | { .compatible = "qcom,sm6115-qusb2-phy", .data = (ulong)&sm6115_phy_cfg }, |
Caleb Connolly | 78fdfd9 | 2023-09-04 15:54:10 +0100 | [diff] [blame^] | 461 | { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg }, |
Bhupesh Sharma | 2e5c2fe | 2023-04-04 02:01:20 +0530 | [diff] [blame] | 462 | { } |
| 463 | }; |
| 464 | |
| 465 | U_BOOT_DRIVER(qcom_qusb2_phy) = { |
| 466 | .name = "qcom-qusb2-phy", |
| 467 | .id = UCLASS_PHY, |
| 468 | .of_match = qusb2phy_ids, |
| 469 | .ops = &qusb2phy_ops, |
| 470 | .probe = qusb2phy_probe, |
| 471 | .priv_auto = sizeof(struct qusb2_phy), |
| 472 | }; |