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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass91785f72015-01-27 22:13:39 -07002/*
3 * Copyright (C) 2015, Google, Inc
4 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass91785f72015-01-27 22:13:39 -07005 */
6
7#include <common.h>
Simon Glassb7c6bae2017-07-30 19:24:01 -07008#include <dm.h>
Simon Glass91785f72015-01-27 22:13:39 -07009#include <errno.h>
Simon Glassdba7ee42020-07-07 21:32:12 -060010#include <log.h>
Simon Glass91785f72015-01-27 22:13:39 -070011#include <malloc.h>
Simon Glassb7c6bae2017-07-30 19:24:01 -070012#include <mapmem.h>
Simon Glass91785f72015-01-27 22:13:39 -070013#include <sdhci.h>
Simon Glassdba7ee42020-07-07 21:32:12 -060014#include <acpi/acpigen.h>
15#include <acpi/acpi_device.h>
16#include <acpi/acpi_dp.h>
17#include <asm-generic/gpio.h>
18#include <dm/acpi.h>
Simon Glass91785f72015-01-27 22:13:39 -070019
Simon Glassb7c6bae2017-07-30 19:24:01 -070020struct pci_mmc_plat {
21 struct mmc_config cfg;
22 struct mmc mmc;
23};
24
25struct pci_mmc_priv {
26 struct sdhci_host host;
27 void *base;
Simon Glassdba7ee42020-07-07 21:32:12 -060028 struct gpio_desc cd_gpio;
Simon Glassb7c6bae2017-07-30 19:24:01 -070029};
30
31static int pci_mmc_probe(struct udevice *dev)
Simon Glass91785f72015-01-27 22:13:39 -070032{
Simon Glassb7c6bae2017-07-30 19:24:01 -070033 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -070034 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glassb7c6bae2017-07-30 19:24:01 -070035 struct pci_mmc_priv *priv = dev_get_priv(dev);
36 struct sdhci_host *host = &priv->host;
Simon Glass91785f72015-01-27 22:13:39 -070037 int ret;
Simon Glass91785f72015-01-27 22:13:39 -070038
Bernhard Messerklinger0851f342018-02-15 09:09:43 +010039 host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
40 PCI_REGION_MEM);
Simon Glassb7c6bae2017-07-30 19:24:01 -070041 host->name = dev->name;
Peng Fana5abe152019-08-06 02:47:56 +000042 host->mmc = &plat->mmc;
43 host->mmc->dev = dev;
Simon Glassb7c6bae2017-07-30 19:24:01 -070044 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
45 if (ret)
46 return ret;
Simon Glassb7c6bae2017-07-30 19:24:01 -070047 host->mmc->priv = &priv->host;
Simon Glassb7c6bae2017-07-30 19:24:01 -070048 upriv->mmc = host->mmc;
Simon Glass91785f72015-01-27 22:13:39 -070049
Simon Glassb7c6bae2017-07-30 19:24:01 -070050 return sdhci_probe(dev);
Simon Glass91785f72015-01-27 22:13:39 -070051}
Simon Glassb7c6bae2017-07-30 19:24:01 -070052
Simon Glassd1998a92020-12-03 16:55:21 -070053static int pci_mmc_of_to_plat(struct udevice *dev)
Simon Glassdba7ee42020-07-07 21:32:12 -060054{
Harm Berntsen7b4fe6d2020-11-06 12:20:44 +000055 if (CONFIG_IS_ENABLED(DM_GPIO)) {
56 struct pci_mmc_priv *priv = dev_get_priv(dev);
Simon Glassdba7ee42020-07-07 21:32:12 -060057
Harm Berntsen7b4fe6d2020-11-06 12:20:44 +000058 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
59 }
Simon Glassdba7ee42020-07-07 21:32:12 -060060
61 return 0;
62}
63
Simon Glassb7c6bae2017-07-30 19:24:01 -070064static int pci_mmc_bind(struct udevice *dev)
65{
Simon Glassc69cda22020-12-03 16:55:20 -070066 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glassb7c6bae2017-07-30 19:24:01 -070067
68 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
69}
70
Simon Glassdba7ee42020-07-07 21:32:12 -060071static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
72 struct acpi_ctx *ctx)
73{
74 struct pci_mmc_priv *priv = dev_get_priv(dev);
75 char path[ACPI_PATH_MAX];
76 struct acpi_gpio gpio;
77 struct acpi_dp *dp;
78 int ret;
79
Simon Glass7d14ee42020-12-19 10:40:13 -070080 if (!dev_has_ofnode(dev))
Simon Glassdba7ee42020-07-07 21:32:12 -060081 return 0;
82
83 ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
84 if (ret)
85 return log_msg_ret("gpio", ret);
86 gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
87 gpio.pull = ACPI_GPIO_PULL_NONE;
88 gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
89 gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
90 gpio.irq.shared = ACPI_IRQ_SHARED;
91 gpio.irq.wake = ACPI_IRQ_WAKE;
92 gpio.interrupt_debounce_timeout = 10000; /* 100ms */
93
94 /* Use device path as the Scope for the SSDT */
95 ret = acpi_device_path(dev, path, sizeof(path));
96 if (ret)
97 return log_msg_ret("path", ret);
98 acpigen_write_scope(ctx, path);
99 acpigen_write_name(ctx, "_CRS");
100
101 /* Write GpioInt() as default (if set) or custom from devicetree */
102 acpigen_write_resourcetemplate_header(ctx);
103 acpi_device_write_gpio(ctx, &gpio);
104 acpigen_write_resourcetemplate_footer(ctx);
105
106 /* Bind the cd-gpio name to the GpioInt() resource */
107 dp = acpi_dp_new_table("_DSD");
108 if (!dp)
109 return -ENOMEM;
110 acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
111 ret = acpi_dp_write(ctx, dp);
112 if (ret)
113 return log_msg_ret("cd", ret);
114
115 acpigen_pop_len(ctx);
116
117 return 0;
118}
119
120struct acpi_ops pci_mmc_acpi_ops = {
121 .fill_ssdt = pci_mmc_acpi_fill_ssdt,
122};
123
124static const struct udevice_id pci_mmc_match[] = {
125 { .compatible = "intel,apl-sd" },
126 { }
127};
128
Simon Glassb7c6bae2017-07-30 19:24:01 -0700129U_BOOT_DRIVER(pci_mmc) = {
130 .name = "pci_mmc",
131 .id = UCLASS_MMC,
Simon Glassdba7ee42020-07-07 21:32:12 -0600132 .of_match = pci_mmc_match,
Simon Glassb7c6bae2017-07-30 19:24:01 -0700133 .bind = pci_mmc_bind,
Simon Glassd1998a92020-12-03 16:55:21 -0700134 .of_to_plat = pci_mmc_of_to_plat,
Simon Glassb7c6bae2017-07-30 19:24:01 -0700135 .probe = pci_mmc_probe,
136 .ops = &sdhci_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700137 .priv_auto = sizeof(struct pci_mmc_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700138 .plat_auto = sizeof(struct pci_mmc_plat),
Simon Glassdba7ee42020-07-07 21:32:12 -0600139 ACPI_OPS_PTR(&pci_mmc_acpi_ops)
Simon Glassb7c6bae2017-07-30 19:24:01 -0700140};
141
142static struct pci_device_id mmc_supported[] = {
Bin Menga191cca2017-08-09 00:21:00 -0700143 { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDHCI << 8, 0xffff00) },
Simon Glassb7c6bae2017-07-30 19:24:01 -0700144 {},
145};
146
147U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);