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Scott Woodc97cd1b2012-09-20 19:02:18 -05001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de
4 *
5 * Copyright 2009 Freescale Semiconductor, Inc.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Scott Woodc97cd1b2012-09-20 19:02:18 -05008 */
9
Masahiro Yamada6f2ed0e2014-04-28 10:17:10 +090010#include "config.h"
Scott Woodc97cd1b2012-09-20 19:02:18 -050011
12OUTPUT_ARCH(powerpc)
Ying Zhang5df572f2013-05-20 14:07:23 +080013#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
14PHDRS
15{
16 text PT_LOAD;
17 bss PT_LOAD;
18}
19#endif
Scott Woodc97cd1b2012-09-20 19:02:18 -050020SECTIONS
21{
22 . = CONFIG_SPL_TEXT_BASE;
23 .text : {
24 *(.text*)
25 }
26 _etext = .;
27
28 .reloc : {
29 _GOT2_TABLE_ = .;
30 KEEP(*(.got2))
31 KEEP(*(.got))
Scott Woodc97cd1b2012-09-20 19:02:18 -050032 _FIXUP_TABLE_ = .;
33 KEEP(*(.fixup))
34 }
35 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
36 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
37
38 . = ALIGN(8);
39 .data : {
40 *(.rodata*)
41 *(.data*)
42 *(.sdata*)
43 }
44 _edata = .;
45
Ying Zhang81b867a2013-09-04 17:03:45 +080046 . = ALIGN(4);
47 .u_boot_list : {
48 KEEP(*(SORT(.u_boot_list*)));
49 }
50
Ying Zhangbb0dc102013-08-16 15:16:11 +080051 . = .;
52 __start___ex_table = .;
53 __ex_table : { *(__ex_table) }
54 __stop___ex_table = .;
55
Scott Woodc97cd1b2012-09-20 19:02:18 -050056 . = ALIGN(8);
57 __init_begin = .;
58 __init_end = .;
Prabhakar Kushwaha651fcf62014-04-08 19:12:31 +053059#ifdef CONFIG_SPL_SKIP_RELOCATE
60 . = ALIGN(4);
61 __bss_start = .;
62 .bss : {
63 *(.sbss*)
64 *(.bss*)
65 }
66 . = ALIGN(4);
67 __bss_end = .;
68#endif
Po Liu66099162014-01-10 10:10:58 +080069
70/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
71#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
72 .bootpg ADDR(.text) - 0x1000 :
73 {
74 KEEP(*(.bootpg))
75 } :text = 0xffff
76#else
Scott Woodc97cd1b2012-09-20 19:02:18 -050077#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
Prabhakar Kushwaha49efe85b2014-04-08 19:12:19 +053078#ifndef BOOT_PAGE_OFFSET
79#define BOOT_PAGE_OFFSET 0x1000
80#endif
81 .bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
Scott Woodc97cd1b2012-09-20 19:02:18 -050082 {
Prabhakar Kushwaha3a881792013-04-16 13:27:59 +053083 arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
Scott Woodc97cd1b2012-09-20 19:02:18 -050084 }
Prabhakar Kushwaha49efe85b2014-04-08 19:12:19 +053085#ifndef RESET_VECTOR_OFFSET
Scott Woodc97cd1b2012-09-20 19:02:18 -050086#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
Prabhakar Kushwaha49efe85b2014-04-08 19:12:19 +053087#endif
Scott Woodc97cd1b2012-09-20 19:02:18 -050088#elif defined(CONFIG_FSL_ELBC)
89#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
90#else
91#error unknown NAND controller
92#endif
93 .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
94 KEEP(*(.resetvec))
95 } = 0xffff
Ying Zhang5df572f2013-05-20 14:07:23 +080096#endif
Scott Woodc97cd1b2012-09-20 19:02:18 -050097
Prabhakar Kushwaha651fcf62014-04-08 19:12:31 +053098#ifndef CONFIG_SPL_SKIP_RELOCATE
Scott Woodc97cd1b2012-09-20 19:02:18 -050099 /*
100 * Make sure that the bss segment isn't linked at 0x0, otherwise its
101 * address won't be updated during relocation fixups.
102 */
103 . |= 0x10;
104
Ying Zhang67ad0d52013-06-07 17:25:16 +0800105 . = ALIGN(4);
Scott Woodc97cd1b2012-09-20 19:02:18 -0500106 __bss_start = .;
107 .bss : {
108 *(.sbss*)
109 *(.bss*)
110 }
Ying Zhang67ad0d52013-06-07 17:25:16 +0800111 . = ALIGN(4);
Simon Glass3929fb02013-03-14 06:54:53 +0000112 __bss_end = .;
Prabhakar Kushwaha651fcf62014-04-08 19:12:31 +0530113#endif
Scott Woodc97cd1b2012-09-20 19:02:18 -0500114}