blob: 800b98ff98afcfff81f9639cb710e55b845369a1 [file] [log] [blame]
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Configuation settings for the SAM9X60EK board.
4 *
5 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
8 */
9
10#ifndef __CONFIG_H__
11#define __CONFIG_H__
12
13/* ARM asynchronous clock */
Tom Rini65cc0e22022-11-16 13:10:41 -050014#define CFG_SYS_AT91_SLOW_CLOCK 32768
15#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000016
Tom Rini805482d2022-12-04 10:14:02 -050017#define CFG_USART_BASE ATMEL_BASE_DBGU
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000018#define CONFIG_USART_ID 0 /* ignored in arm */
19
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000020/*
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000021 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
22 * NB: in this case, USB 1.1 devices won't be recognized.
23 */
24
25/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -050026#define CFG_SYS_SDRAM_BASE 0x20000000
27#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000028
Tudor Ambarus8ed15e42019-09-27 13:09:07 +000029/* NAND flash */
30#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -050031#define CFG_SYS_NAND_BASE 0x40000000
32#define CFG_SYS_NAND_MASK_ALE BIT(21)
33#define CFG_SYS_NAND_MASK_CLE BIT(22)
34#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
35#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
Tudor Ambarus8ed15e42019-09-27 13:09:07 +000036#endif
37
Sandeep Sheriker Mallikarjun51422662019-09-27 13:08:52 +000038#endif