blob: 4d2af483d77f07688e6a4297a1ad952ea0d9a99a [file] [log] [blame]
Allen Martin77c42e82013-03-16 18:58:13 +00001/*
2 * NVIDIA Tegra SPI controller (T114 and later)
3 *
4 * Copyright (c) 2010-2013 NVIDIA Corporation
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <asm/io.h>
27#include <asm/gpio.h>
28#include <asm/arch/clock.h>
29#include <asm/arch-tegra/clk_rst.h>
30#include <asm/arch-tegra114/tegra114_spi.h>
31#include <spi.h>
32#include <fdtdec.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36/* COMMAND1 */
37#define SPI_CMD1_GO (1 << 31)
38#define SPI_CMD1_M_S (1 << 30)
39#define SPI_CMD1_MODE_MASK 0x3
40#define SPI_CMD1_MODE_SHIFT 28
41#define SPI_CMD1_CS_SEL_MASK 0x3
42#define SPI_CMD1_CS_SEL_SHIFT 26
43#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
44#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
45#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
46#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
47#define SPI_CMD1_CS_SW_HW (1 << 21)
48#define SPI_CMD1_CS_SW_VAL (1 << 20)
49#define SPI_CMD1_IDLE_SDA_MASK 0x3
50#define SPI_CMD1_IDLE_SDA_SHIFT 18
51#define SPI_CMD1_BIDIR (1 << 17)
52#define SPI_CMD1_LSBI_FE (1 << 16)
53#define SPI_CMD1_LSBY_FE (1 << 15)
54#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
55#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
56#define SPI_CMD1_RX_EN (1 << 12)
57#define SPI_CMD1_TX_EN (1 << 11)
58#define SPI_CMD1_PACKED (1 << 5)
59#define SPI_CMD1_BIT_LEN_MASK 0x1F
60#define SPI_CMD1_BIT_LEN_SHIFT 0
61
62/* COMMAND2 */
63#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
64#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
65#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
66#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
67
68/* TRANSFER STATUS */
69#define SPI_XFER_STS_RDY (1 << 30)
70
71/* FIFO STATUS */
72#define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
73#define SPI_FIFO_STS_FRAME_END (1 << 30)
74#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
75#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
76#define SPI_FIFO_STS_ERR (1 << 8)
77#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
78#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
79#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
80#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
81#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
82#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
83#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
84#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
85
86#define SPI_TIMEOUT 1000
87#define TEGRA_SPI_MAX_FREQ 52000000
88
89struct spi_regs {
90 u32 command1; /* 000:SPI_COMMAND1 register */
91 u32 command2; /* 004:SPI_COMMAND2 register */
92 u32 timing1; /* 008:SPI_CS_TIM1 register */
93 u32 timing2; /* 00c:SPI_CS_TIM2 register */
94 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
95 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
96 u32 tx_data; /* 018:SPI_TX_DATA register */
97 u32 rx_data; /* 01c:SPI_RX_DATA register */
98 u32 dma_ctl; /* 020:SPI_DMA_CTL register */
99 u32 dma_blk; /* 024:SPI_DMA_BLK register */
100 u32 rsvd[56]; /* 028-107 reserved */
101 u32 tx_fifo; /* 108:SPI_FIFO1 register */
102 u32 rsvd2[31]; /* 10c-187 reserved */
103 u32 rx_fifo; /* 188:SPI_FIFO2 register */
104 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
105};
106
107struct tegra_spi_ctrl {
108 struct spi_regs *regs;
109 unsigned int freq;
110 unsigned int mode;
111 int periph_id;
112 int valid;
113};
114
115struct tegra_spi_slave {
116 struct spi_slave slave;
117 struct tegra_spi_ctrl *ctrl;
118};
119
120static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
121
122static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
123{
124 return container_of(slave, struct tegra_spi_slave, slave);
125}
126
127int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
128{
129 if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
130 return 0;
131 else
132 return 1;
133}
134
135struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
136 unsigned int max_hz, unsigned int mode)
137{
138 struct tegra_spi_slave *spi;
139
140 debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
141 bus, cs, max_hz, mode);
142
143 if (!spi_cs_is_valid(bus, cs)) {
144 printf("SPI error: unsupported bus %d / chip select %d\n",
145 bus, cs);
146 return NULL;
147 }
148
149 if (max_hz > TEGRA_SPI_MAX_FREQ) {
150 printf("SPI error: unsupported frequency %d Hz. Max frequency"
151 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
152 return NULL;
153 }
154
Axel Lind6f64d42013-06-13 16:17:47 +0800155 spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
Allen Martin77c42e82013-03-16 18:58:13 +0000156 if (!spi) {
157 printf("SPI error: malloc of SPI structure failed\n");
158 return NULL;
159 }
Allen Martin77c42e82013-03-16 18:58:13 +0000160 spi->ctrl = &spi_ctrls[bus];
161 if (!spi->ctrl) {
162 printf("SPI error: could not find controller for bus %d\n",
163 bus);
164 return NULL;
165 }
166
167 if (max_hz < spi->ctrl->freq) {
168 debug("%s: limiting frequency from %u to %u\n", __func__,
169 spi->ctrl->freq, max_hz);
170 spi->ctrl->freq = max_hz;
171 }
172 spi->ctrl->mode = mode;
173
174 return &spi->slave;
175}
176
177void tegra114_spi_free_slave(struct spi_slave *slave)
178{
179 struct tegra_spi_slave *spi = to_tegra_spi(slave);
180
181 free(spi);
182}
183
184int tegra114_spi_init(int *node_list, int count)
185{
186 struct tegra_spi_ctrl *ctrl;
187 int i;
188 int node = 0;
189 int found = 0;
190
191 for (i = 0; i < count; i++) {
192 ctrl = &spi_ctrls[i];
193 node = node_list[i];
194
195 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
196 node, "reg");
197 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
198 debug("%s: no spi register found\n", __func__);
199 continue;
200 }
201 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
202 "spi-max-frequency", 0);
203 if (!ctrl->freq) {
204 debug("%s: no spi max frequency found\n", __func__);
205 continue;
206 }
207
208 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
209 if (ctrl->periph_id == PERIPH_ID_NONE) {
210 debug("%s: could not decode periph id\n", __func__);
211 continue;
212 }
213 ctrl->valid = 1;
214 found = 1;
215
216 debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
217 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
218 }
219
220 return !found;
221}
222
223int tegra114_spi_claim_bus(struct spi_slave *slave)
224{
225 struct tegra_spi_slave *spi = to_tegra_spi(slave);
226 struct spi_regs *regs = spi->ctrl->regs;
227
228 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
229 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
230 spi->ctrl->freq);
231
232 /* Clear stale status here */
233 setbits_le32(&regs->fifo_status,
234 SPI_FIFO_STS_ERR |
235 SPI_FIFO_STS_TX_FIFO_OVF |
236 SPI_FIFO_STS_TX_FIFO_UNR |
237 SPI_FIFO_STS_RX_FIFO_OVF |
238 SPI_FIFO_STS_RX_FIFO_UNR |
239 SPI_FIFO_STS_TX_FIFO_FULL |
240 SPI_FIFO_STS_TX_FIFO_EMPTY |
241 SPI_FIFO_STS_RX_FIFO_FULL |
242 SPI_FIFO_STS_RX_FIFO_EMPTY);
243 debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
244
245 /* Set master mode and sw controlled CS */
246 setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
247 (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
248 debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
249
250 return 0;
251}
252
253void tegra114_spi_cs_activate(struct spi_slave *slave)
254{
255 struct tegra_spi_slave *spi = to_tegra_spi(slave);
256 struct spi_regs *regs = spi->ctrl->regs;
257
258 clrbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
259}
260
261void tegra114_spi_cs_deactivate(struct spi_slave *slave)
262{
263 struct tegra_spi_slave *spi = to_tegra_spi(slave);
264 struct spi_regs *regs = spi->ctrl->regs;
265
266 setbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
267}
268
269int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
270 const void *data_out, void *data_in, unsigned long flags)
271{
272 struct tegra_spi_slave *spi = to_tegra_spi(slave);
273 struct spi_regs *regs = spi->ctrl->regs;
274 u32 reg, tmpdout, tmpdin = 0;
275 const u8 *dout = data_out;
276 u8 *din = data_in;
277 int num_bytes;
278 int ret;
279
280 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
281 __func__, slave->bus, slave->cs, dout, din, bitlen);
282 if (bitlen % 8)
283 return -1;
284 num_bytes = bitlen / 8;
285
286 ret = 0;
287
288 /* clear all error status bits */
289 reg = readl(&regs->fifo_status);
290 writel(reg, &regs->fifo_status);
291
292 /* clear ready bit */
293 setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
294
295 clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
296 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
297 (slave->cs << SPI_CMD1_CS_SEL_SHIFT));
298
299 /* set xfer size to 1 block (32 bits) */
300 writel(0, &regs->dma_blk);
301
302 if (flags & SPI_XFER_BEGIN)
303 spi_cs_activate(slave);
304
305 /* handle data in 32-bit chunks */
306 while (num_bytes > 0) {
307 int bytes;
308 int is_read = 0;
309 int tm, i;
310
311 tmpdout = 0;
312 bytes = (num_bytes > 4) ? 4 : num_bytes;
313
314 if (dout != NULL) {
315 for (i = 0; i < bytes; ++i)
316 tmpdout = (tmpdout << 8) | dout[i];
317 dout += bytes;
318 }
319
320 num_bytes -= bytes;
321
322 clrsetbits_le32(&regs->command1,
323 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
324 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
325 writel(tmpdout, &regs->tx_fifo);
326 setbits_le32(&regs->command1, SPI_CMD1_GO);
327
328 /*
329 * Wait for SPI transmit FIFO to empty, or to time out.
330 * The RX FIFO status will be read and cleared last
331 */
332 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
333 u32 fifo_status, xfer_status;
334
335 fifo_status = readl(&regs->fifo_status);
336
337 /* We can exit when we've had both RX and TX activity */
338 if (is_read &&
339 (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY))
340 break;
341
342 xfer_status = readl(&regs->xfer_status);
343 if (!(xfer_status & SPI_XFER_STS_RDY))
344 continue;
345
346 if (fifo_status & SPI_FIFO_STS_ERR) {
347 debug("%s: got a fifo error: ", __func__);
348 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
349 debug("tx FIFO overflow ");
350 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
351 debug("tx FIFO underrun ");
352 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
353 debug("rx FIFO overflow ");
354 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
355 debug("rx FIFO underrun ");
356 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
357 debug("tx FIFO full ");
358 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
359 debug("tx FIFO empty ");
360 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
361 debug("rx FIFO full ");
362 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
363 debug("rx FIFO empty ");
364 debug("\n");
365 break;
366 }
367
368 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
369 tmpdin = readl(&regs->rx_fifo);
370 is_read = 1;
371
372 /* swap bytes read in */
373 if (din != NULL) {
374 for (i = bytes - 1; i >= 0; --i) {
375 din[i] = tmpdin & 0xff;
376 tmpdin >>= 8;
377 }
378 din += bytes;
379 }
380 }
381 }
382
383 if (tm >= SPI_TIMEOUT)
384 ret = tm;
385
386 /* clear ACK RDY, etc. bits */
387 writel(readl(&regs->fifo_status), &regs->fifo_status);
388 }
389
390 if (flags & SPI_XFER_END)
391 spi_cs_deactivate(slave);
392
393 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
394 __func__, tmpdin, readl(&regs->fifo_status));
395
396 if (ret) {
397 printf("%s: timeout during SPI transfer, tm %d\n",
398 __func__, ret);
399 return -1;
400 }
401
402 return 0;
403}