| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Po-Yu Chuang | 43a5f0d | 2009-11-11 17:27:30 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 Faraday Technology |
| 4 | * Po-Yu Chuang <ratbert@faraday-tech.com> |
| Po-Yu Chuang | 43a5f0d | 2009-11-11 17:27:30 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * SDRAM Controller |
| 9 | */ |
| 10 | #ifndef __FTSDMC020_H |
| 11 | #define __FTSDMC020_H |
| 12 | |
| 13 | #define FTSDMC020_OFFSET_TP0 0x00 |
| 14 | #define FTSDMC020_OFFSET_TP1 0x04 |
| 15 | #define FTSDMC020_OFFSET_CR 0x08 |
| 16 | #define FTSDMC020_OFFSET_BANK0_BSR 0x0C |
| 17 | #define FTSDMC020_OFFSET_BANK1_BSR 0x10 |
| 18 | #define FTSDMC020_OFFSET_BANK2_BSR 0x14 |
| 19 | #define FTSDMC020_OFFSET_BANK3_BSR 0x18 |
| 20 | #define FTSDMC020_OFFSET_BANK4_BSR 0x1C |
| 21 | #define FTSDMC020_OFFSET_BANK5_BSR 0x20 |
| 22 | #define FTSDMC020_OFFSET_BANK6_BSR 0x24 |
| 23 | #define FTSDMC020_OFFSET_BANK7_BSR 0x28 |
| 24 | #define FTSDMC020_OFFSET_ACR 0x34 |
| 25 | |
| 26 | /* |
| 27 | * Timing Parametet 0 Register |
| 28 | */ |
| 29 | #define FTSDMC020_TP0_TCL(x) ((x) & 0x3) |
| 30 | #define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) |
| 31 | #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) |
| 32 | #define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) |
| 33 | #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) |
| 34 | #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) |
| 35 | |
| 36 | /* |
| 37 | * Timing Parametet 1 Register |
| 38 | */ |
| 39 | #define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) |
| 40 | #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) |
| 41 | #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) |
| 42 | |
| 43 | /* |
| 44 | * Configuration Register |
| 45 | */ |
| 46 | #define FTSDMC020_CR_SREF (1 << 0) |
| 47 | #define FTSDMC020_CR_PWDN (1 << 1) |
| 48 | #define FTSDMC020_CR_ISMR (1 << 2) |
| 49 | #define FTSDMC020_CR_IREF (1 << 3) |
| 50 | #define FTSDMC020_CR_IPREC (1 << 4) |
| 51 | #define FTSDMC020_CR_REFTYPE (1 << 5) |
| 52 | |
| 53 | /* |
| 54 | * SDRAM External Bank Base/Size Register |
| 55 | */ |
| 56 | #define FTSDMC020_BANK_ENABLE (1 << 28) |
| 57 | |
| 58 | #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) |
| 59 | |
| 60 | #define FTSDMC020_BANK_DDW_X4 (0 << 12) |
| 61 | #define FTSDMC020_BANK_DDW_X8 (1 << 12) |
| 62 | #define FTSDMC020_BANK_DDW_X16 (2 << 12) |
| 63 | #define FTSDMC020_BANK_DDW_X32 (3 << 12) |
| 64 | |
| 65 | #define FTSDMC020_BANK_DSZ_16M (0 << 8) |
| 66 | #define FTSDMC020_BANK_DSZ_64M (1 << 8) |
| 67 | #define FTSDMC020_BANK_DSZ_128M (2 << 8) |
| 68 | #define FTSDMC020_BANK_DSZ_256M (3 << 8) |
| 69 | |
| 70 | #define FTSDMC020_BANK_MBW_8 (0 << 4) |
| 71 | #define FTSDMC020_BANK_MBW_16 (1 << 4) |
| 72 | #define FTSDMC020_BANK_MBW_32 (2 << 4) |
| 73 | |
| 74 | #define FTSDMC020_BANK_SIZE_1M 0x0 |
| 75 | #define FTSDMC020_BANK_SIZE_2M 0x1 |
| 76 | #define FTSDMC020_BANK_SIZE_4M 0x2 |
| 77 | #define FTSDMC020_BANK_SIZE_8M 0x3 |
| 78 | #define FTSDMC020_BANK_SIZE_16M 0x4 |
| 79 | #define FTSDMC020_BANK_SIZE_32M 0x5 |
| 80 | #define FTSDMC020_BANK_SIZE_64M 0x6 |
| 81 | #define FTSDMC020_BANK_SIZE_128M 0x7 |
| 82 | #define FTSDMC020_BANK_SIZE_256M 0x8 |
| 83 | |
| 84 | /* |
| 85 | * Arbiter Control Register |
| 86 | */ |
| 87 | #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) |
| 88 | #define FTSDMC020_ACR_TOE (1 << 8) |
| 89 | |
| 90 | #endif /* __FTSDMC020_H */ |