| Kristoffer Ericson | 80bf2bb | 2010-10-15 23:31:43 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Memory Setup stuff - taken from blob memsetup.S |
| 3 | * |
| 4 | * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and |
| 5 | * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) |
| 6 | * 2004 (c) MontaVista Software, Inc. |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | |
| 28 | #include "config.h" |
| 29 | #include "version.h" |
| 30 | |
| 31 | |
| 32 | /*----------------------------------------------------------------------- |
| 33 | * Board defines: |
| 34 | */ |
| 35 | |
| 36 | #define MDCNFG 0x00 |
| 37 | #define MDCAS00 0x04 |
| 38 | #define MDCAS01 0x08 |
| 39 | #define MDCAS02 0x0C |
| 40 | #define MSC0 0x10 |
| 41 | #define MSC1 0x14 |
| 42 | #define MECR 0x18 |
| 43 | #define MDREFR 0x1C |
| 44 | #define MDCAS20 0x20 |
| 45 | #define MDCAS21 0x24 |
| 46 | #define MDCAS22 0x28 |
| 47 | #define MSC2 0x2C |
| 48 | #define SMCNFG 0x30 |
| 49 | |
| 50 | #define GPDR 0x04 |
| 51 | #define GPSR 0x08 |
| 52 | #define GPCR 0x0C |
| 53 | #define GAFR 0x1C |
| 54 | |
| 55 | #define PPDR 0x00 |
| 56 | #define PPSR 0x04 |
| 57 | #define PPAR 0x08 |
| 58 | |
| 59 | #define MDREFR_TRASR(n_) (n_ & (0x0000000f)) |
| 60 | #define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4) |
| 61 | #define MDREFR_K0DB2 (1 << 18) |
| 62 | #define MDREFR_K1DB2 (1 << 22) |
| 63 | #define MDREFR_K2DB2 (1 << 26) |
| 64 | |
| 65 | #define MDREFR_K0RUN (1 << 17) |
| 66 | #define MDREFR_K1RUN (1 << 21) |
| 67 | #define MDREFR_K2RUN (1 << 25) |
| 68 | |
| 69 | #define MDREFR_SLFRSH (1 << 31) |
| 70 | #define MDREFR_E1PIN (1 << 20) |
| 71 | |
| 72 | #define PSSR 0x04 |
| 73 | #define PSSR_DH 0x00000008 |
| 74 | #define POSR 0x08 |
| 75 | #define RCSR 0x04 |
| 76 | |
| 77 | /*----------------------------------------------------------------------- |
| 78 | * Setup parameters for the board: |
| 79 | */ |
| 80 | MEM_BASE: .long 0xa0000000 |
| 81 | MEM_START: .long 0xc0000000 |
| 82 | PWR_BASE: .word 0x90020000 |
| 83 | RST_BASE: .long 0x90030000 |
| 84 | PPC_BASE: .long 0x90060000 |
| 85 | GPIO_BASE: .long 0x90040000 |
| 86 | IC_BASE: .word 0x90050000 |
| 87 | |
| 88 | cpuspeed: .word 0xa0 |
| 89 | /* calculated from old blob bootloader */ |
| 90 | mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */ |
| 91 | mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */ |
| 92 | mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */ |
| 93 | mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */ |
| 94 | msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */ |
| 95 | msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */ |
| 96 | mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */ |
| 97 | mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */ |
| 98 | mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */ |
| 99 | mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */ |
| 100 | mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */ |
| 101 | msc2: .long 0x201d2959 /* msc2 0x201d2959 */ |
| 102 | smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */ |
| 103 | |
| 104 | pin_set_out: .long 0x37ff70 |
| 105 | pin_set_dir: .long 0x11480 |
| 106 | |
| 107 | gpdr_set: .long 0x0B3A0900 |
| 108 | gpsr_set: .long 0x02100800 |
| 109 | gpcr_set: .long 0x092A0100 |
| 110 | gafr_set: .long 0x08600000 |
| 111 | |
| 112 | .globl lowlevel_init |
| 113 | lowlevel_init: |
| 114 | |
| 115 | /* set output and direction of pins */ |
| 116 | ldr r0, PPC_BASE |
| 117 | ldr r1, pin_set_out |
| 118 | str r1, [r0, #PPSR] |
| 119 | ldr r1, pin_set_dir |
| 120 | str r1, [r0, #PPDR] |
| 121 | |
| 122 | /* Setting up the memory and stuff */ |
| 123 | /***********************************/ |
| 124 | |
| 125 | ldr r0, MEM_BASE |
| 126 | |
| 127 | ldr r1, mdcnfg |
| 128 | str r1, [r0, #MDCNFG] |
| 129 | ldr r1, mdcas00 |
| 130 | str r1, [r0, #MDCAS00] |
| 131 | ldr r1, mdcas01 |
| 132 | str r1, [r0, #MDCAS01] |
| 133 | ldr r1, mdcas02 |
| 134 | str r1, [r0, #MDCAS02] |
| 135 | ldr r1, mdcas20 |
| 136 | str r1, [r0, #MDCAS20] |
| 137 | ldr r1, mdcas21 |
| 138 | str r1, [r0, #MDCAS21] |
| 139 | ldr r1, mdcas22 |
| 140 | str r1, [r0, #MDCAS22] |
| 141 | |
| 142 | /* clear kxDB2 */ |
| 143 | ldr r2, [r0, #MDREFR] |
| 144 | bic r2, r2, #MDREFR_K0DB2 |
| 145 | bic r2, r2, #MDREFR_K1DB2 |
| 146 | bic r2, r2, #MDREFR_K2DB2 |
| 147 | str r2, [r0, #MDREFR] |
| 148 | |
| 149 | ldr r2, [r0, #MDREFR] |
| 150 | orr r2, r2, #MDREFR_TRASR(7) |
| 151 | |
| 152 | mov r4, #0x2000 |
| 153 | spin: subs r4, r4, #1 |
| 154 | bne spin |
| 155 | |
| 156 | ldr r1, PWR_BASE |
| 157 | mov r2, #PSSR_DH |
| 158 | str r2, [r1, #PSSR] |
| 159 | |
| 160 | ldr r2, [r0, #MDREFR] |
| 161 | bic r2, r2, #MDREFR_K0DB2 |
| 162 | bic r2, r2, #MDREFR_K1DB2 |
| 163 | bic r2, r2, #MDREFR_K2DB2 |
| 164 | str r2, [r0, #MDREFR] |
| 165 | |
| 166 | ldr r2, [r0, #MDREFR] |
| 167 | orr r2, r2, #MDREFR_TRASR(7) |
| 168 | orr r2, r2, #MDREFR_DRI(12) |
| 169 | orr r2, r2, #MDREFR_K0DB2 |
| 170 | orr r2, r2, #MDREFR_K1DB2 |
| 171 | orr r2, r2, #MDREFR_K2DB2 |
| 172 | str r2, [r0, #MDREFR] |
| 173 | |
| 174 | ldr r2, [r0, #MDREFR] |
| 175 | orr r2, r2, #MDREFR_K0RUN |
| 176 | orr r2, r2, #MDREFR_K1RUN |
| 177 | orr r2, r2, #MDREFR_K2RUN |
| 178 | str r2, [r0, #MDREFR] |
| 179 | |
| 180 | ldr r2, [r0, #MDREFR] |
| 181 | bic r2, r2, #MDREFR_SLFRSH |
| 182 | str r2, [r0, #MDREFR] |
| 183 | |
| 184 | ldr r2, [r0, #MDREFR] |
| 185 | orr r2, r2, #MDREFR_E1PIN |
| 186 | str r2, [r0, #MDREFR] |
| 187 | |
| 188 | ldr r2, MEM_START |
| 189 | .rept 8 |
| 190 | ldr r3, [r2] |
| 191 | .endr |
| 192 | |
| 193 | ldr r1, msc0 |
| 194 | str r1, [r0, #MSC0] |
| 195 | ldr r1, msc1 |
| 196 | str r1, [r0, #MSC1] |
| 197 | ldr r1, msc2 |
| 198 | str r1, [r0, #MSC2] |
| 199 | ldr r1, smcnfg |
| 200 | str r1, [r0, #SMCNFG] |
| 201 | ldr r1, mdcnfg |
| 202 | str r1, [r0, #MDCNFG] |
| 203 | ldr r1, mecr |
| 204 | str r1, [r0, #MECR] |
| 205 | |
| 206 | /* enable SDRAM */ |
| 207 | orr r1, r1, #0x00000001 |
| 208 | str r1, [r0, #MDCNFG] |
| 209 | |
| 210 | mov pc, lr |