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Ilya Yanokeb819552012-11-06 13:48:21 +00001/*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_REGS_H__
36#define __MUSB_REGS_H__
37
38#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
39
40/*
41 * MUSB Register bits
42 */
43
44/* POWER */
45#define MUSB_POWER_ISOUPDATE 0x80
46#define MUSB_POWER_SOFTCONN 0x40
47#define MUSB_POWER_HSENAB 0x20
48#define MUSB_POWER_HSMODE 0x10
49#define MUSB_POWER_RESET 0x08
50#define MUSB_POWER_RESUME 0x04
51#define MUSB_POWER_SUSPENDM 0x02
52#define MUSB_POWER_ENSUSPEND 0x01
53
54/* INTRUSB */
55#define MUSB_INTR_SUSPEND 0x01
56#define MUSB_INTR_RESUME 0x02
57#define MUSB_INTR_RESET 0x04
58#define MUSB_INTR_BABBLE 0x04
59#define MUSB_INTR_SOF 0x08
60#define MUSB_INTR_CONNECT 0x10
61#define MUSB_INTR_DISCONNECT 0x20
62#define MUSB_INTR_SESSREQ 0x40
63#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
64
65/* DEVCTL */
66#define MUSB_DEVCTL_BDEVICE 0x80
67#define MUSB_DEVCTL_FSDEV 0x40
68#define MUSB_DEVCTL_LSDEV 0x20
69#define MUSB_DEVCTL_VBUS 0x18
70#define MUSB_DEVCTL_VBUS_SHIFT 3
71#define MUSB_DEVCTL_HM 0x04
72#define MUSB_DEVCTL_HR 0x02
73#define MUSB_DEVCTL_SESSION 0x01
74
75/* MUSB ULPI VBUSCONTROL */
76#define MUSB_ULPI_USE_EXTVBUS 0x01
77#define MUSB_ULPI_USE_EXTVBUSIND 0x02
78/* ULPI_REG_CONTROL */
79#define MUSB_ULPI_REG_REQ (1 << 0)
80#define MUSB_ULPI_REG_CMPLT (1 << 1)
81#define MUSB_ULPI_RDN_WR (1 << 2)
82
83/* TESTMODE */
84#define MUSB_TEST_FORCE_HOST 0x80
85#define MUSB_TEST_FIFO_ACCESS 0x40
86#define MUSB_TEST_FORCE_FS 0x20
87#define MUSB_TEST_FORCE_HS 0x10
88#define MUSB_TEST_PACKET 0x08
89#define MUSB_TEST_K 0x04
90#define MUSB_TEST_J 0x02
91#define MUSB_TEST_SE0_NAK 0x01
92
93/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
94#define MUSB_FIFOSZ_DPB 0x10
95/* Allocation size (8, 16, 32, ... 4096) */
96#define MUSB_FIFOSZ_SIZE 0x0f
97
98/* CSR0 */
99#define MUSB_CSR0_FLUSHFIFO 0x0100
100#define MUSB_CSR0_TXPKTRDY 0x0002
101#define MUSB_CSR0_RXPKTRDY 0x0001
102
103/* CSR0 in Peripheral mode */
104#define MUSB_CSR0_P_SVDSETUPEND 0x0080
105#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
106#define MUSB_CSR0_P_SENDSTALL 0x0020
107#define MUSB_CSR0_P_SETUPEND 0x0010
108#define MUSB_CSR0_P_DATAEND 0x0008
109#define MUSB_CSR0_P_SENTSTALL 0x0004
110
111/* CSR0 in Host mode */
112#define MUSB_CSR0_H_DIS_PING 0x0800
113#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
114#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
115#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
116#define MUSB_CSR0_H_STATUSPKT 0x0040
117#define MUSB_CSR0_H_REQPKT 0x0020
118#define MUSB_CSR0_H_ERROR 0x0010
119#define MUSB_CSR0_H_SETUPPKT 0x0008
120#define MUSB_CSR0_H_RXSTALL 0x0004
121
122/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
123#define MUSB_CSR0_P_WZC_BITS \
124 (MUSB_CSR0_P_SENTSTALL)
125#define MUSB_CSR0_H_WZC_BITS \
126 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
127 | MUSB_CSR0_RXPKTRDY)
128
129/* TxType/RxType */
130#define MUSB_TYPE_SPEED 0xc0
131#define MUSB_TYPE_SPEED_SHIFT 6
132#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
133#define MUSB_TYPE_PROTO_SHIFT 4
134#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
135
136/* CONFIGDATA */
137#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
138#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
139#define MUSB_CONFIGDATA_BIGENDIAN 0x20
140#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
141#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
142#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
143#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
144#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
145
146/* TXCSR in Peripheral and Host mode */
147#define MUSB_TXCSR_AUTOSET 0x8000
148#define MUSB_TXCSR_DMAENAB 0x1000
149#define MUSB_TXCSR_FRCDATATOG 0x0800
150#define MUSB_TXCSR_DMAMODE 0x0400
151#define MUSB_TXCSR_CLRDATATOG 0x0040
152#define MUSB_TXCSR_FLUSHFIFO 0x0008
153#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
154#define MUSB_TXCSR_TXPKTRDY 0x0001
155
156/* TXCSR in Peripheral mode */
157#define MUSB_TXCSR_P_ISO 0x4000
158#define MUSB_TXCSR_P_INCOMPTX 0x0080
159#define MUSB_TXCSR_P_SENTSTALL 0x0020
160#define MUSB_TXCSR_P_SENDSTALL 0x0010
161#define MUSB_TXCSR_P_UNDERRUN 0x0004
162
163/* TXCSR in Host mode */
164#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
165#define MUSB_TXCSR_H_DATATOGGLE 0x0100
166#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
167#define MUSB_TXCSR_H_RXSTALL 0x0020
168#define MUSB_TXCSR_H_ERROR 0x0004
169
170/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
171#define MUSB_TXCSR_P_WZC_BITS \
172 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
173 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
174#define MUSB_TXCSR_H_WZC_BITS \
175 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
176 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
177
178/* RXCSR in Peripheral and Host mode */
179#define MUSB_RXCSR_AUTOCLEAR 0x8000
180#define MUSB_RXCSR_DMAENAB 0x2000
181#define MUSB_RXCSR_DISNYET 0x1000
182#define MUSB_RXCSR_PID_ERR 0x1000
183#define MUSB_RXCSR_DMAMODE 0x0800
184#define MUSB_RXCSR_INCOMPRX 0x0100
185#define MUSB_RXCSR_CLRDATATOG 0x0080
186#define MUSB_RXCSR_FLUSHFIFO 0x0010
187#define MUSB_RXCSR_DATAERROR 0x0008
188#define MUSB_RXCSR_FIFOFULL 0x0002
189#define MUSB_RXCSR_RXPKTRDY 0x0001
190
191/* RXCSR in Peripheral mode */
192#define MUSB_RXCSR_P_ISO 0x4000
193#define MUSB_RXCSR_P_SENTSTALL 0x0040
194#define MUSB_RXCSR_P_SENDSTALL 0x0020
195#define MUSB_RXCSR_P_OVERRUN 0x0004
196
197/* RXCSR in Host mode */
198#define MUSB_RXCSR_H_AUTOREQ 0x4000
199#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
200#define MUSB_RXCSR_H_DATATOGGLE 0x0200
201#define MUSB_RXCSR_H_RXSTALL 0x0040
202#define MUSB_RXCSR_H_REQPKT 0x0020
203#define MUSB_RXCSR_H_ERROR 0x0004
204
205/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
206#define MUSB_RXCSR_P_WZC_BITS \
207 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
208 | MUSB_RXCSR_RXPKTRDY)
209#define MUSB_RXCSR_H_WZC_BITS \
210 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
211 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
212
213/* HUBADDR */
214#define MUSB_HUBADDR_MULTI_TT 0x80
215
216
217#ifndef CONFIG_BLACKFIN
218
Hans de Goede0f8bc532015-01-11 20:34:47 +0100219/* SUNXI has different reg addresses, but identical r/w functions */
220#ifndef CONFIG_ARCH_SUNXI
221
Ilya Yanokeb819552012-11-06 13:48:21 +0000222/*
223 * Common USB registers
224 */
225
226#define MUSB_FADDR 0x00 /* 8-bit */
227#define MUSB_POWER 0x01 /* 8-bit */
228
229#define MUSB_INTRTX 0x02 /* 16-bit */
230#define MUSB_INTRRX 0x04
231#define MUSB_INTRTXE 0x06
232#define MUSB_INTRRXE 0x08
233#define MUSB_INTRUSB 0x0A /* 8 bit */
234#define MUSB_INTRUSBE 0x0B /* 8 bit */
235#define MUSB_FRAME 0x0C
236#define MUSB_INDEX 0x0E /* 8 bit */
237#define MUSB_TESTMODE 0x0F /* 8 bit */
238
239/* Get offset for a given FIFO from musb->mregs */
240#if defined(CONFIG_USB_MUSB_TUSB6010) || \
241 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
242#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
243#else
244#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
245#endif
246
247/*
248 * Additional Control Registers
249 */
250
251#define MUSB_DEVCTL 0x60 /* 8 bit */
252
253/* These are always controlled through the INDEX register */
254#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
255#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
256#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
257#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
258
259/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
260#define MUSB_HWVERS 0x6C /* 8 bit */
261#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
262#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
263#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
264#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
265#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
266#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
267#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
268
269#define MUSB_EPINFO 0x78 /* 8 bit */
270#define MUSB_RAMINFO 0x79 /* 8 bit */
271#define MUSB_LINKINFO 0x7a /* 8 bit */
272#define MUSB_VPLEN 0x7b /* 8 bit */
273#define MUSB_HS_EOF1 0x7c /* 8 bit */
274#define MUSB_FS_EOF1 0x7d /* 8 bit */
275#define MUSB_LS_EOF1 0x7e /* 8 bit */
276
277/* Offsets to endpoint registers */
278#define MUSB_TXMAXP 0x00
279#define MUSB_TXCSR 0x02
280#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
281#define MUSB_RXMAXP 0x04
282#define MUSB_RXCSR 0x06
283#define MUSB_RXCOUNT 0x08
284#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
285#define MUSB_TXTYPE 0x0A
286#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
287#define MUSB_TXINTERVAL 0x0B
288#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
289#define MUSB_RXTYPE 0x0C
290#define MUSB_RXINTERVAL 0x0D
291#define MUSB_FIFOSIZE 0x0F
292#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
293
294/* Offsets to endpoint registers in indexed model (using INDEX register) */
295#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
296 (0x10 + (_offset))
297
298/* Offsets to endpoint registers in flat models */
299#define MUSB_FLAT_OFFSET(_epnum, _offset) \
300 (0x100 + (0x10*(_epnum)) + (_offset))
301
302#if defined(CONFIG_USB_MUSB_TUSB6010) || \
303 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
304/* TUSB6010 EP0 configuration register is special */
305#define MUSB_TUSB_OFFSET(_epnum, _offset) \
306 (0x10 + _offset)
307#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
308#endif
309
310#define MUSB_TXCSR_MODE 0x2000
311
312/* "bus control"/target registers, for host side multipoint (external hubs) */
313#define MUSB_TXFUNCADDR 0x00
314#define MUSB_TXHUBADDR 0x02
315#define MUSB_TXHUBPORT 0x03
316
317#define MUSB_RXFUNCADDR 0x04
318#define MUSB_RXHUBADDR 0x06
319#define MUSB_RXHUBPORT 0x07
320
321#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
322 (0x80 + (8*(_epnum)) + (_offset))
323
Hans de Goede0f8bc532015-01-11 20:34:47 +0100324#else /* CONFIG_ARCH_SUNXI */
325
326/*
327 * Common USB registers
328 */
329
330#define MUSB_FADDR 0x0098
331#define MUSB_POWER 0x0040
332
333#define MUSB_INTRTX 0x0044
334#define MUSB_INTRRX 0x0046
335#define MUSB_INTRTXE 0x0048
336#define MUSB_INTRRXE 0x004A
337#define MUSB_INTRUSB 0x004C
338#define MUSB_INTRUSBE 0x0050
339#define MUSB_FRAME 0x0054
340#define MUSB_INDEX 0x0042
341#define MUSB_TESTMODE 0x007C
342
343/* Get offset for a given FIFO from musb->mregs */
344#define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4))
345
346/*
347 * Additional Control Registers
348 */
349
350#define MUSB_DEVCTL 0x0041
351
352/* These are always controlled through the INDEX register */
353#define MUSB_TXFIFOSZ 0x0090
354#define MUSB_RXFIFOSZ 0x0094
355#define MUSB_TXFIFOADD 0x0092
356#define MUSB_RXFIFOADD 0x0096
357
358#define MUSB_EPINFO 0x0078
359#define MUSB_RAMINFO 0x0079
360#define MUSB_LINKINFO 0x007A
361#define MUSB_VPLEN 0x007B
362#define MUSB_HS_EOF1 0x007C
363#define MUSB_FS_EOF1 0x007D
364#define MUSB_LS_EOF1 0x007E
365
366/* Offsets to endpoint registers */
367#define MUSB_TXMAXP 0x0080
368#define MUSB_TXCSR 0x0082
369#define MUSB_CSR0 0x0082
370#define MUSB_RXMAXP 0x0084
371#define MUSB_RXCSR 0x0086
372#define MUSB_RXCOUNT 0x0088
373#define MUSB_COUNT0 0x0088
374#define MUSB_TXTYPE 0x008C
375#define MUSB_TYPE0 0x008C
376#define MUSB_TXINTERVAL 0x008D
377#define MUSB_NAKLIMIT0 0x008D
378#define MUSB_RXTYPE 0x008E
379#define MUSB_RXINTERVAL 0x008F
380
381#define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */
382#define MUSB_FIFOSIZE 0x0090
383
384/* Offsets to endpoint registers in indexed model (using INDEX register) */
385#define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset)
386
387#define MUSB_TXCSR_MODE 0x2000
388
389/* "bus control"/target registers, for host side multipoint (external hubs) */
390#define MUSB_TXFUNCADDR 0x0098
391#define MUSB_TXHUBADDR 0x009A
392#define MUSB_TXHUBPORT 0x009B
393
394#define MUSB_RXFUNCADDR 0x009C
395#define MUSB_RXHUBADDR 0x009E
396#define MUSB_RXHUBPORT 0x009F
397
398/* Endpoint is selected with MUSB_INDEX. */
399#define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset)
400
401#endif /* CONFIG_ARCH_SUNXI */
402
Ilya Yanokeb819552012-11-06 13:48:21 +0000403static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
404{
405 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
406}
407
408static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
409{
410 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
411}
412
413static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
414{
415 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
416}
417
418static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
419{
420 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
421}
422
423static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
424{
Hans de Goede0f8bc532015-01-11 20:34:47 +0100425#ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
Ilya Yanokeb819552012-11-06 13:48:21 +0000426 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
Hans de Goede0f8bc532015-01-11 20:34:47 +0100427#endif
Ilya Yanokeb819552012-11-06 13:48:21 +0000428}
429
430static inline u8 musb_read_txfifosz(void __iomem *mbase)
431{
432 return musb_readb(mbase, MUSB_TXFIFOSZ);
433}
434
435static inline u16 musb_read_txfifoadd(void __iomem *mbase)
436{
437 return musb_readw(mbase, MUSB_TXFIFOADD);
438}
439
440static inline u8 musb_read_rxfifosz(void __iomem *mbase)
441{
442 return musb_readb(mbase, MUSB_RXFIFOSZ);
443}
444
445static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
446{
447 return musb_readw(mbase, MUSB_RXFIFOADD);
448}
449
450static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
451{
Hans de Goede0f8bc532015-01-11 20:34:47 +0100452#ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
453 return 0;
454#else
Ilya Yanokeb819552012-11-06 13:48:21 +0000455 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
Hans de Goede0f8bc532015-01-11 20:34:47 +0100456#endif
Ilya Yanokeb819552012-11-06 13:48:21 +0000457}
458
459static inline u8 musb_read_configdata(void __iomem *mbase)
460{
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530461#ifdef CONFIG_MACH_SUN8I_A33
462 /* <Sigh> allwinner saves a reg, and we need to hardcode this */
463 return 0xde;
464#else
Ilya Yanokeb819552012-11-06 13:48:21 +0000465 musb_writeb(mbase, MUSB_INDEX, 0);
466 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530467#endif
Ilya Yanokeb819552012-11-06 13:48:21 +0000468}
469
470static inline u16 musb_read_hwvers(void __iomem *mbase)
471{
Hans de Goede0f8bc532015-01-11 20:34:47 +0100472#ifdef CONFIG_ARCH_SUNXI
473 return 0; /* Unknown version */
474#else
Ilya Yanokeb819552012-11-06 13:48:21 +0000475 return musb_readw(mbase, MUSB_HWVERS);
Hans de Goede0f8bc532015-01-11 20:34:47 +0100476#endif
Ilya Yanokeb819552012-11-06 13:48:21 +0000477}
478
479static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
480{
481 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
482}
483
484static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
485 u8 qh_addr_reg)
486{
487 musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
488}
489
490static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
491 u8 qh_h_addr_reg)
492{
493 musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
494}
495
496static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
497 u8 qh_h_port_reg)
498{
499 musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
500}
501
502static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
503 u8 qh_addr_reg)
504{
505 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
506 qh_addr_reg);
507}
508
509static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
510 u8 qh_addr_reg)
511{
512 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
513 qh_addr_reg);
514}
515
516static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
517 u8 qh_h_port_reg)
518{
519 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
520 qh_h_port_reg);
521}
522
523static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
524{
525 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
526}
527
528static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
529{
530 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
531}
532
533static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
534{
535 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
536}
537
538static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
539{
540 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
541}
542
543static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
544{
545 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
546}
547
548static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
549{
550 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
551}
552
553#else /* CONFIG_BLACKFIN */
554
555#define USB_BASE USB_FADDR
556#define USB_OFFSET(reg) (reg - USB_BASE)
557
558/*
559 * Common USB registers
560 */
561#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
562#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
563#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
564#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
565#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
566#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
567#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
568#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
569#define MUSB_FRAME USB_OFFSET(USB_FRAME)
570#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
571#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
572
573/* Get offset for a given FIFO from musb->mregs */
574#define MUSB_FIFO_OFFSET(epnum) \
575 (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
576
577/*
578 * Additional Control Registers
579 */
580
581#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
582
583#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
584#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
585#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
586#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
587#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
588
589/* Offsets to endpoint registers */
590#define MUSB_TXMAXP 0x00
591#define MUSB_TXCSR 0x04
592#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
593#define MUSB_RXMAXP 0x08
594#define MUSB_RXCSR 0x0C
595#define MUSB_RXCOUNT 0x10
596#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
597#define MUSB_TXTYPE 0x14
598#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
599#define MUSB_TXINTERVAL 0x18
600#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
601#define MUSB_RXTYPE 0x1C
602#define MUSB_RXINTERVAL 0x20
603#define MUSB_TXCOUNT 0x28
604
605/* Offsets to endpoint registers in indexed model (using INDEX register) */
606#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
607 (0x40 + (_offset))
608
609/* Offsets to endpoint registers in flat models */
610#define MUSB_FLAT_OFFSET(_epnum, _offset) \
611 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
612
613/* Not implemented - HW has separate Tx/Rx FIFO */
614#define MUSB_TXCSR_MODE 0x0000
615
616static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
617{
618}
619
620static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
621{
622}
623
624static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
625{
626}
627
628static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
629{
630}
631
632static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
633{
634}
635
636static inline u8 musb_read_txfifosz(void __iomem *mbase)
637{
638 return 0;
639}
640
641static inline u16 musb_read_txfifoadd(void __iomem *mbase)
642{
643 return 0;
644}
645
646static inline u8 musb_read_rxfifosz(void __iomem *mbase)
647{
648 return 0;
649}
650
651static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
652{
653 return 0;
654}
655
656static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
657{
658 return 0;
659}
660
661static inline u8 musb_read_configdata(void __iomem *mbase)
662{
663 return 0;
664}
665
666static inline u16 musb_read_hwvers(void __iomem *mbase)
667{
668 /*
669 * This register is invisible on Blackfin, actually the MUSB
670 * RTL version of Blackfin is 1.9, so just harcode its value.
671 */
672 return MUSB_HWVERS_1900;
673}
674
675static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
676{
677 return NULL;
678}
679
680static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
681 u8 qh_addr_req)
682{
683}
684
685static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
686 u8 qh_h_addr_reg)
687{
688}
689
690static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
691 u8 qh_h_port_reg)
692{
693}
694
695static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
696 u8 qh_addr_reg)
697{
698}
699
700static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
701 u8 qh_addr_reg)
702{
703}
704
705static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
706 u8 qh_h_port_reg)
707{
708}
709
710static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
711{
712 return 0;
713}
714
715static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
716{
717 return 0;
718}
719
720static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
721{
722 return 0;
723}
724
725static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
726{
727 return 0;
728}
729
730static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
731{
732 return 0;
733}
734
735static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
736{
737 return 0;
738}
739
740#endif /* CONFIG_BLACKFIN */
741
742#endif /* __MUSB_REGS_H__ */