blob: 6676f373f2f67525fe0e3e8712fb8f06ad240378 [file] [log] [blame]
wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk7abf0c52004-04-18 21:45:42 +000011 */
12
13/* mpc8560ads board configuration file */
14/* please refer to doc/README.mpc85xx for more info */
15/* make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050016 * search for CONFIG_SERVERIP, etc. in this file
wdenk7abf0c52004-04-18 21:45:42 +000017 */
18
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/* High Level Configuration Options */
23#define CONFIG_BOOKE 1 /* BOOKE */
24#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050025#define CONFIG_CPM2 1 /* has CPM2 */
wdenk7abf0c52004-04-18 21:45:42 +000026#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050027#define CONFIG_MPC8560 1
wdenk7abf0c52004-04-18 21:45:42 +000028
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xfff80000
30
Wolfgang Denk53677ef2008-05-20 16:00:29 +020031#undef CONFIG_PCI /* pci ethernet support */
32#define CONFIG_TSEC_ENET /* tsec ethernet support*/
wdenk7abf0c52004-04-18 21:45:42 +000033#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
34#define CONFIG_ENV_OVERWRITE
wdenk7abf0c52004-04-18 21:45:42 +000035
Kumar Gala572b13a2008-01-16 09:11:53 -060036#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk9aea9532004-08-01 23:02:45 +000037
38/* sysclk for MPC85xx
wdenk7abf0c52004-04-18 21:45:42 +000039 */
wdenk7abf0c52004-04-18 21:45:42 +000040
41#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
42
43/* Blinkin' LEDs for Robert :-)
44*/
45#define CONFIG_SHOW_ACTIVITY 1
46
wdenk9aea9532004-08-01 23:02:45 +000047/*
48 * These can be toggled for performance analysis, otherwise use default.
49 */
wdenk7abf0c52004-04-18 21:45:42 +000050#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk9aea9532004-08-01 23:02:45 +000051#define CONFIG_BTB /* toggle branch predition */
wdenk7abf0c52004-04-18 21:45:42 +000052
wdenk9aea9532004-08-01 23:02:45 +000053#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Peter Tyser004eca02009-09-16 22:03:08 -050054#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk7abf0c52004-04-18 21:45:42 +000055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
57#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
58#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk7abf0c52004-04-18 21:45:42 +000059
wdenk7abf0c52004-04-18 21:45:42 +000060
61/* Localbus SDRAM is an option, not all boards have it.
wdenk9aea9532004-08-01 23:02:45 +000062 * This address, however, is used to configure a 256M local bus
63 * window that includes the Config latch below.
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
66#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk7abf0c52004-04-18 21:45:42 +000067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
69#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk7abf0c52004-04-18 21:45:42 +000070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
72#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
73#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
74#undef CONFIG_SYS_FLASH_CHECKSUM
75#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
76#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk7abf0c52004-04-18 21:45:42 +000077
78/* The configuration latch is Chip Select 1.
wdenk9aea9532004-08-01 23:02:45 +000079 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk7abf0c52004-04-18 21:45:42 +000080 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
82#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
83#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
wdenk7abf0c52004-04-18 21:45:42 +000084
Wolfgang Denk14d0a022010-10-07 21:51:12 +020085#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk7abf0c52004-04-18 21:45:42 +000086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
88#define CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +000089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +000091#endif
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#ifdef CONFIG_SYS_RAMBOOT
94#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
wdenk7abf0c52004-04-18 21:45:42 +000095#endif
Timur Tabie46fedf2011-08-04 18:03:41 -050096#define CONFIG_SYS_CCSRBAR 0xfdf00000
97#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk7abf0c52004-04-18 21:45:42 +000098
Kumar Galac360d9b2008-08-27 01:03:42 -050099/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700100#define CONFIG_SYS_FSL_DDR1
Kumar Galac360d9b2008-08-27 01:03:42 -0500101#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
102#define CONFIG_DDR_SPD
103#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk7abf0c52004-04-18 21:45:42 +0000104
Kumar Galac360d9b2008-08-27 01:03:42 -0500105#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Becky Bruce810c4422010-12-17 17:17:58 -0600106#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
Kumar Galac360d9b2008-08-27 01:03:42 -0500107#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk7abf0c52004-04-18 21:45:42 +0000108
Kumar Galac360d9b2008-08-27 01:03:42 -0500109#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000113
Kumar Galac360d9b2008-08-27 01:03:42 -0500114#define CONFIG_NUM_DDR_CONTROLLERS 1
115#define CONFIG_DIMM_SLOTS_PER_CTLR 1
116#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
117
118/* I2C addresses of SPD EEPROMs */
119#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
wdenk7abf0c52004-04-18 21:45:42 +0000120
121#undef CONFIG_CLOCKS_IN_MHZ
122
123/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
125#define CONFIG_SYS_OR2_PRELIM 0xfc006901
126#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
127#define CONFIG_SYS_LBC_LBCR 0x00000000
128#define CONFIG_SYS_LBC_LSRT 0x20000000
129#define CONFIG_SYS_LBC_MRTPR 0x20000000
130#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
131#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
132#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
133#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
134#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk7abf0c52004-04-18 21:45:42 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_RAM_LOCK 1
137#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200138#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk7abf0c52004-04-18 21:45:42 +0000139
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200140#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7abf0c52004-04-18 21:45:42 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
144#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk7abf0c52004-04-18 21:45:42 +0000145
146/* Serial Port */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200147#define CONFIG_CONS_ON_SCC /* define if console on SCC */
148#undef CONFIG_CONS_NONE /* define if console on something else */
149#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
wdenk7abf0c52004-04-18 21:45:42 +0000150
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200151#define CONFIG_BAUDRATE 38400
wdenk7abf0c52004-04-18 21:45:42 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7abf0c52004-04-18 21:45:42 +0000154 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
155
156/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HUSH_PARSER
158#ifdef CONFIG_SYS_HUSH_PARSER
wdenk7abf0c52004-04-18 21:45:42 +0000159#endif
160
Jon Loeliger20476722006-10-20 15:50:15 -0500161/*
162 * I2C
163 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200164#define CONFIG_SYS_I2C
165#define CONFIG_SYS_I2C_FSL
166#define CONFIG_SYS_FSL_I2C_SPEED 400000
167#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
168#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
169
wdenk7abf0c52004-04-18 21:45:42 +0000170#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
wdenk7abf0c52004-04-18 21:45:42 +0000172#else
173/* I did the 'if 0' so we could keep the syntax above if ever needed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#undef CONFIG_SYS_I2C_NOPROBES
wdenk7abf0c52004-04-18 21:45:42 +0000175#endif
176
wdenk9aea9532004-08-01 23:02:45 +0000177/* RapdIO Map configuration, mapped 1:1.
178*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
180#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
181#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
wdenk9aea9532004-08-01 23:02:45 +0000182
183/* Standard 8560 PCI addressing, mapped 1:1.
184*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
186#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
187#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
188#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
189#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
190#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk7abf0c52004-04-18 21:45:42 +0000191
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200192#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk9aea9532004-08-01 23:02:45 +0000193
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200194#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk9aea9532004-08-01 23:02:45 +0000195
196#undef CONFIG_EEPRO100
197#undef CONFIG_TULIP
198
199#if !defined(CONFIG_PCI_PNP)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200200 #define PCI_ENET0_IOADDR 0xe0000000
wdenk7abf0c52004-04-18 21:45:42 +0000201 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200202 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk7abf0c52004-04-18 21:45:42 +0000203#endif
wdenk9aea9532004-08-01 23:02:45 +0000204
205#undef CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk9aea9532004-08-01 23:02:45 +0000207
208#endif /* CONFIG_PCI */
209
210#if defined(CONFIG_TSEC_ENET)
211
wdenk7abf0c52004-04-18 21:45:42 +0000212#define CONFIG_MII 1 /* MII PHY management */
wdenk9aea9532004-08-01 23:02:45 +0000213
Kim Phillips255a35772007-05-16 16:52:19 -0500214#define CONFIG_TSEC1 1
215#define CONFIG_TSEC1_NAME "TSEC0"
216#define CONFIG_TSEC2 1
217#define CONFIG_TSEC2_NAME "TSEC1"
wdenk9aea9532004-08-01 23:02:45 +0000218
219#define TSEC1_PHY_ADDR 2
220#define TSEC2_PHY_ADDR 4
221#define TSEC1_PHYIDX 0
222#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500223#define TSEC1_FLAGS TSEC_GIGABIT
224#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500225#define CONFIG_ETHPRIME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000226
wdenk7abf0c52004-04-18 21:45:42 +0000227#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk9aea9532004-08-01 23:02:45 +0000228
wdenk7abf0c52004-04-18 21:45:42 +0000229#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
230#undef CONFIG_ETHER_NONE /* define if ether on something else */
231#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk9aea9532004-08-01 23:02:45 +0000232
233#if (CONFIG_ETHER_INDEX == 2)
wdenk7abf0c52004-04-18 21:45:42 +0000234 /*
235 * - Rx-CLK is CLK13
236 * - Tx-CLK is CLK14
237 * - Select bus for bd/buffers
238 * - Full duplex
239 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000240 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
241 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenk7abf0c52004-04-18 21:45:42 +0000243#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk7abf0c52004-04-18 21:45:42 +0000245#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 #define CONFIG_SYS_FCC_PSMR 0
wdenk7abf0c52004-04-18 21:45:42 +0000247#endif
248 #define FETH2_RST 0x01
wdenk9aea9532004-08-01 23:02:45 +0000249#elif (CONFIG_ETHER_INDEX == 3)
wdenk7abf0c52004-04-18 21:45:42 +0000250 /* need more definitions here for FE3 */
251 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200252#endif /* CONFIG_ETHER_INDEX */
wdenk9aea9532004-08-01 23:02:45 +0000253
254/* MDIO is done through the TSEC0 control.
255*/
wdenk7abf0c52004-04-18 21:45:42 +0000256#define CONFIG_MII /* MII PHY management */
257#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk7abf0c52004-04-18 21:45:42 +0000258
wdenk7abf0c52004-04-18 21:45:42 +0000259#endif
260
261/* Environment */
262/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk7abf0c52004-04-18 21:45:42 +0000263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200265 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200267 #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
268 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200271 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200273 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000274#endif
275
276#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk9aea9532004-08-01 23:02:45 +0000277#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk7abf0c52004-04-18 21:45:42 +0000278#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
279
280#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7abf0c52004-04-18 21:45:42 +0000282
Jon Loeliger2835e512007-06-13 13:22:08 -0500283/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500284 * BOOTP options
285 */
286#define CONFIG_BOOTP_BOOTFILESIZE
287#define CONFIG_BOOTP_BOOTPATH
288#define CONFIG_BOOTP_GATEWAY
289#define CONFIG_BOOTP_HOSTNAME
290
291
292/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500293 * Command line configuration.
294 */
Jon Loeliger2835e512007-06-13 13:22:08 -0500295#define CONFIG_CMD_PING
296#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500297#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500298
Joe Hershbergeref0f2f52015-06-22 16:15:30 -0500299#if !defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger2835e512007-06-13 13:22:08 -0500300 #define CONFIG_CMD_ELF
wdenk7abf0c52004-04-18 21:45:42 +0000301#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500302
303#if defined(CONFIG_PCI)
304 #define CONFIG_CMD_PCI
305#endif
306
307#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
308 #define CONFIG_CMD_MII
309#endif
310
wdenk7abf0c52004-04-18 21:45:42 +0000311
312#undef CONFIG_WATCHDOG /* watchdog disabled */
313
314/*
315 * Miscellaneous configurable options
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_LONGHELP /* undef to save memory */
318#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500319#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000321#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000323#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
325#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
326#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
327#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk7abf0c52004-04-18 21:45:42 +0000328
329/*
330 * For booting Linux, the board info and command line data
331 * have to be in the first 8 MB of memory, since this is
332 * the maximum mapped by the Linux kernel during initialization.
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7abf0c52004-04-18 21:45:42 +0000335
Jon Loeliger2835e512007-06-13 13:22:08 -0500336#if defined(CONFIG_CMD_KGDB)
wdenk7abf0c52004-04-18 21:45:42 +0000337#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk7abf0c52004-04-18 21:45:42 +0000338#endif
339
wdenk7abf0c52004-04-18 21:45:42 +0000340#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500341#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000342#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000343#define CONFIG_HAS_ETH2
wdenk7abf0c52004-04-18 21:45:42 +0000344#endif
345
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200346#define CONFIG_SERVERIP 192.168.85.1
347#define CONFIG_IPADDR 192.168.85.60
wdenk7abf0c52004-04-18 21:45:42 +0000348#define CONFIG_GATEWAYIP 192.168.85.1
349#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200350#define CONFIG_HOSTNAME STX_GP3
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000351#define CONFIG_ROOTPATH "/gppproot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000352#define CONFIG_BOOTFILE "uImage"
wdenk9aea9532004-08-01 23:02:45 +0000353#define CONFIG_LOADADDR 0x1000000
wdenk7abf0c52004-04-18 21:45:42 +0000354
355#endif /* __CONFIG_H */