Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 2 | /* |
Bin Meng | bfa95c5 | 2015-10-11 21:37:38 -0700 | [diff] [blame] | 3 | * From coreboot src/southbridge/intel/bd82x6x/mrccache.c |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2014 Google Inc. |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 6 | * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com> |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 10 | #include <dm.h> |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 11 | #include <errno.h> |
| 12 | #include <fdtdec.h> |
| 13 | #include <net.h> |
| 14 | #include <spi.h> |
| 15 | #include <spi_flash.h> |
Bin Meng | f6220f1 | 2015-10-11 21:37:36 -0700 | [diff] [blame] | 16 | #include <asm/mrccache.h> |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 17 | #include <dm/device-internal.h> |
| 18 | #include <dm/uclass-internal.h> |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 19 | |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
Simon Glass | ca4e408 | 2019-09-25 08:57:04 -0600 | [diff] [blame] | 22 | static uint mrc_block_size(uint data_size) |
| 23 | { |
| 24 | uint mrc_size = sizeof(struct mrc_data_container) + data_size; |
| 25 | |
| 26 | return ALIGN(mrc_size, MRC_DATA_ALIGN); |
| 27 | } |
| 28 | |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 29 | static struct mrc_data_container *next_mrc_block( |
Bin Meng | bfa95c5 | 2015-10-11 21:37:38 -0700 | [diff] [blame] | 30 | struct mrc_data_container *cache) |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 31 | { |
| 32 | /* MRC data blocks are aligned within the region */ |
Bin Meng | bfa95c5 | 2015-10-11 21:37:38 -0700 | [diff] [blame] | 33 | u8 *region_ptr = (u8 *)cache; |
| 34 | |
Simon Glass | ca4e408 | 2019-09-25 08:57:04 -0600 | [diff] [blame] | 35 | region_ptr += mrc_block_size(cache->data_size); |
Bin Meng | bfa95c5 | 2015-10-11 21:37:38 -0700 | [diff] [blame] | 36 | |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 37 | return (struct mrc_data_container *)region_ptr; |
| 38 | } |
| 39 | |
| 40 | static int is_mrc_cache(struct mrc_data_container *cache) |
| 41 | { |
| 42 | return cache && (cache->signature == MRC_DATA_SIGNATURE); |
| 43 | } |
| 44 | |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 45 | struct mrc_data_container *mrccache_find_current(struct mrc_region *entry) |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 46 | { |
| 47 | struct mrc_data_container *cache, *next; |
| 48 | ulong base_addr, end_addr; |
| 49 | uint id; |
| 50 | |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 51 | base_addr = entry->base + entry->offset; |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 52 | end_addr = base_addr + entry->length; |
| 53 | cache = NULL; |
| 54 | |
| 55 | /* Search for the last filled entry in the region */ |
| 56 | for (id = 0, next = (struct mrc_data_container *)base_addr; |
| 57 | is_mrc_cache(next); |
| 58 | id++) { |
| 59 | cache = next; |
| 60 | next = next_mrc_block(next); |
| 61 | if ((ulong)next >= end_addr) |
| 62 | break; |
| 63 | } |
| 64 | |
| 65 | if (id-- == 0) { |
| 66 | debug("%s: No valid MRC cache found.\n", __func__); |
| 67 | return NULL; |
| 68 | } |
| 69 | |
| 70 | /* Verify checksum */ |
| 71 | if (cache->checksum != compute_ip_checksum(cache->data, |
| 72 | cache->data_size)) { |
| 73 | printf("%s: MRC cache checksum mismatch\n", __func__); |
| 74 | return NULL; |
| 75 | } |
| 76 | |
| 77 | debug("%s: picked entry %u from cache block\n", __func__, id); |
| 78 | |
| 79 | return cache; |
| 80 | } |
| 81 | |
| 82 | /** |
| 83 | * find_next_mrc_cache() - get next cache entry |
| 84 | * |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 85 | * This moves to the next cache entry in the region, making sure it has enough |
| 86 | * space to hold data of size @data_size. |
| 87 | * |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 88 | * @entry: MRC cache flash area |
| 89 | * @cache: Entry to start from |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 90 | * @data_size: Required data size of the new entry. Note that we assume that |
| 91 | * all cache entries are the same size |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 92 | * |
| 93 | * @return next cache entry if found, NULL if we got to the end |
| 94 | */ |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 95 | static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry, |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 96 | struct mrc_data_container *prev, int data_size) |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 97 | { |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 98 | struct mrc_data_container *cache; |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 99 | ulong base_addr, end_addr; |
| 100 | |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 101 | base_addr = entry->base + entry->offset; |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 102 | end_addr = base_addr + entry->length; |
| 103 | |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 104 | /* |
| 105 | * We assume that all cache entries are the same size, but let's use |
| 106 | * data_size here for clarity. |
| 107 | */ |
| 108 | cache = next_mrc_block(prev); |
| 109 | if ((ulong)cache + mrc_block_size(data_size) > end_addr) { |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 110 | /* Crossed the boundary */ |
| 111 | cache = NULL; |
| 112 | debug("%s: no available entries found\n", __func__); |
| 113 | } else { |
| 114 | debug("%s: picked next entry from cache block at %p\n", |
| 115 | __func__, cache); |
| 116 | } |
| 117 | |
| 118 | return cache; |
| 119 | } |
| 120 | |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 121 | int mrccache_update(struct udevice *sf, struct mrc_region *entry, |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 122 | struct mrc_data_container *cur) |
| 123 | { |
| 124 | struct mrc_data_container *cache; |
| 125 | ulong offset; |
| 126 | ulong base_addr; |
| 127 | int ret; |
| 128 | |
Simon Glass | 079b38b | 2019-04-25 21:58:59 -0600 | [diff] [blame] | 129 | if (!is_mrc_cache(cur)) { |
| 130 | debug("%s: Cache data not valid\n", __func__); |
Bin Meng | 2fe66db | 2015-10-11 21:37:37 -0700 | [diff] [blame] | 131 | return -EINVAL; |
Simon Glass | 079b38b | 2019-04-25 21:58:59 -0600 | [diff] [blame] | 132 | } |
Bin Meng | 2fe66db | 2015-10-11 21:37:37 -0700 | [diff] [blame] | 133 | |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 134 | /* Find the last used block */ |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 135 | base_addr = entry->base + entry->offset; |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 136 | debug("Updating MRC cache data\n"); |
| 137 | cache = mrccache_find_current(entry); |
| 138 | if (cache && (cache->data_size == cur->data_size) && |
| 139 | (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) { |
| 140 | debug("MRC data in flash is up to date. No update\n"); |
| 141 | return -EEXIST; |
| 142 | } |
| 143 | |
| 144 | /* Move to the next block, which will be the first unused block */ |
| 145 | if (cache) |
Simon Glass | 0ad9b6a | 2019-12-06 21:42:02 -0700 | [diff] [blame] | 146 | cache = find_next_mrc_cache(entry, cache, cur->data_size); |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 147 | |
| 148 | /* |
| 149 | * If we have got to the end, erase the entire mrc-cache area and start |
| 150 | * again at block 0. |
| 151 | */ |
| 152 | if (!cache) { |
| 153 | debug("Erasing the MRC cache region of %x bytes at %x\n", |
| 154 | entry->length, entry->offset); |
| 155 | |
Simon Glass | ba45756 | 2015-03-26 09:29:26 -0600 | [diff] [blame] | 156 | ret = spi_flash_erase_dm(sf, entry->offset, entry->length); |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 157 | if (ret) { |
| 158 | debug("Failed to erase flash region\n"); |
| 159 | return ret; |
| 160 | } |
| 161 | cache = (struct mrc_data_container *)base_addr; |
| 162 | } |
| 163 | |
| 164 | /* Write the data out */ |
| 165 | offset = (ulong)cache - base_addr + entry->offset; |
| 166 | debug("Write MRC cache update to flash at %lx\n", offset); |
Simon Glass | ba45756 | 2015-03-26 09:29:26 -0600 | [diff] [blame] | 167 | ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur), |
| 168 | cur); |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 169 | if (ret) { |
| 170 | debug("Failed to write to SPI flash\n"); |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 171 | return log_msg_ret("Cannot update mrccache", ret); |
Simon Glass | 191c008 | 2015-01-19 22:16:14 -0700 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | return 0; |
| 175 | } |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 176 | |
Simon Glass | 9a67994 | 2019-04-25 21:58:57 -0600 | [diff] [blame] | 177 | static void mrccache_setup(void *data) |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 178 | { |
Simon Glass | 9a67994 | 2019-04-25 21:58:57 -0600 | [diff] [blame] | 179 | struct mrc_data_container *cache = data; |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 180 | u16 checksum; |
| 181 | |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 182 | cache->signature = MRC_DATA_SIGNATURE; |
| 183 | cache->data_size = gd->arch.mrc_output_len; |
| 184 | checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size); |
| 185 | debug("Saving %d bytes for MRC output data, checksum %04x\n", |
| 186 | cache->data_size, checksum); |
| 187 | cache->checksum = checksum; |
| 188 | cache->reserved = 0; |
| 189 | memcpy(cache->data, gd->arch.mrc_output, cache->data_size); |
| 190 | |
Simon Glass | 37a508f | 2019-12-06 21:42:05 -0700 | [diff] [blame] | 191 | gd->arch.mrc_cache = cache; |
Simon Glass | 9a67994 | 2019-04-25 21:58:57 -0600 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | int mrccache_reserve(void) |
| 195 | { |
| 196 | if (!gd->arch.mrc_output_len) |
| 197 | return 0; |
| 198 | |
| 199 | /* adjust stack pointer to store pure cache data plus the header */ |
| 200 | gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); |
| 201 | mrccache_setup((void *)gd->start_addr_sp); |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 202 | |
| 203 | gd->start_addr_sp &= ~0xf; |
| 204 | |
| 205 | return 0; |
| 206 | } |
| 207 | |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 208 | int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 209 | { |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 210 | struct udevice *dev; |
| 211 | ofnode mrc_node; |
Simon Glass | 506f224 | 2019-12-06 21:42:04 -0700 | [diff] [blame] | 212 | ulong map_base; |
| 213 | uint map_size; |
| 214 | uint offset; |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 215 | u32 reg[2]; |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 216 | int ret; |
| 217 | |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 218 | /* |
| 219 | * Find the flash chip within the SPI controller node. Avoid probing |
| 220 | * the device here since it may put it into a strange state where the |
| 221 | * memory map cannot be read. |
| 222 | */ |
| 223 | ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); |
| 224 | if (ret) |
| 225 | return log_msg_ret("Cannot find SPI flash\n", ret); |
Simon Glass | 506f224 | 2019-12-06 21:42:04 -0700 | [diff] [blame] | 226 | ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset); |
| 227 | if (!ret) { |
| 228 | entry->base = map_base; |
| 229 | } else { |
| 230 | ret = dev_read_u32_array(dev, "memory-map", reg, 2); |
| 231 | if (ret) |
| 232 | return log_msg_ret("Cannot find memory map\n", ret); |
| 233 | entry->base = reg[0]; |
| 234 | } |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 235 | |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 236 | /* Find the place where we put the MRC cache */ |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 237 | mrc_node = dev_read_subnode(dev, "rw-mrc-cache"); |
| 238 | if (!ofnode_valid(mrc_node)) |
| 239 | return log_msg_ret("Cannot find node", -EPERM); |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 240 | |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 241 | ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2); |
| 242 | if (ret) |
| 243 | return log_msg_ret("Cannot find address", ret); |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 244 | entry->offset = reg[0]; |
| 245 | entry->length = reg[1]; |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 246 | |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 247 | if (devp) |
| 248 | *devp = dev; |
Simon Glass | 506f224 | 2019-12-06 21:42:04 -0700 | [diff] [blame] | 249 | debug("MRC cache in '%s', offset %x, len %x, base %x\n", |
| 250 | dev->name, entry->offset, entry->length, entry->base); |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | int mrccache_save(void) |
| 256 | { |
Simon Glass | 37a508f | 2019-12-06 21:42:05 -0700 | [diff] [blame] | 257 | struct mrc_data_container *cache; |
Bin Meng | 4b9f6a6 | 2015-10-11 21:37:41 -0700 | [diff] [blame] | 258 | struct mrc_region entry; |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 259 | struct udevice *sf; |
| 260 | int ret; |
| 261 | |
| 262 | if (!gd->arch.mrc_output_len) |
| 263 | return 0; |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 264 | debug("Saving %#x bytes of MRC output data to SPI flash\n", |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 265 | gd->arch.mrc_output_len); |
| 266 | |
| 267 | ret = mrccache_get_region(&sf, &entry); |
| 268 | if (ret) |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 269 | return log_msg_ret("Cannot get region", ret); |
Simon Glass | 87f1084 | 2019-12-06 21:42:03 -0700 | [diff] [blame] | 270 | ret = device_probe(sf); |
| 271 | if (ret) |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 272 | return log_msg_ret("Cannot probe device", ret); |
Simon Glass | 37a508f | 2019-12-06 21:42:05 -0700 | [diff] [blame] | 273 | cache = gd->arch.mrc_cache; |
| 274 | ret = mrccache_update(sf, &entry, cache); |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 275 | if (!ret) |
Simon Glass | 37a508f | 2019-12-06 21:42:05 -0700 | [diff] [blame] | 276 | debug("Saved MRC data with checksum %04x\n", cache->checksum); |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 277 | else if (ret == -EEXIST) |
Simon Glass | 8b67441 | 2016-01-17 16:11:29 -0700 | [diff] [blame] | 278 | debug("MRC data is the same as last time, skipping save\n"); |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 279 | |
Simon Glass | 83f288f | 2019-12-06 21:42:06 -0700 | [diff] [blame^] | 280 | return 0; |
Bin Meng | ed80096 | 2015-10-11 21:37:39 -0700 | [diff] [blame] | 281 | } |
Simon Glass | 9a67994 | 2019-04-25 21:58:57 -0600 | [diff] [blame] | 282 | |
| 283 | int mrccache_spl_save(void) |
| 284 | { |
| 285 | void *data; |
| 286 | int size; |
| 287 | |
| 288 | size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE; |
| 289 | data = malloc(size); |
| 290 | if (!data) |
| 291 | return log_msg_ret("Allocate MRC cache block", -ENOMEM); |
| 292 | mrccache_setup(data); |
| 293 | gd->arch.mrc_output = data; |
| 294 | |
| 295 | return mrccache_save(); |
| 296 | } |