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wdenk71f95112003-06-15 22:40:42 +00001/*
wdenk8655b6f2004-10-09 23:25:58 +00002 * PXA LCD Controller
3 *
wdenk71f95112003-06-15 22:40:42 +00004 * (C) Copyright 2001-2002
5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************/
27/* ** HEADER FILES */
28/************************************************************************/
29
wdenk71f95112003-06-15 22:40:42 +000030#include <config.h>
31#include <common.h>
32#include <version.h>
33#include <stdarg.h>
wdenk71f95112003-06-15 22:40:42 +000034#include <linux/types.h>
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +020035#include <stdio_dev.h>
wdenk8655b6f2004-10-09 23:25:58 +000036#include <lcd.h>
wdenk71f95112003-06-15 22:40:42 +000037#include <asm/arch/pxa-regs.h>
38
wdenk8655b6f2004-10-09 23:25:58 +000039/* #define DEBUG */
40
wdenk71f95112003-06-15 22:40:42 +000041#ifdef CONFIG_LCD
42
wdenk71f95112003-06-15 22:40:42 +000043/*----------------------------------------------------------------------*/
wdenk71f95112003-06-15 22:40:42 +000044/*
wdenk8655b6f2004-10-09 23:25:58 +000045 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
46 * your display.
wdenk71f95112003-06-15 22:40:42 +000047 */
48
wdenk8655b6f2004-10-09 23:25:58 +000049#ifdef CONFIG_PXA_VGA
50/* LCD outputs connected to a video DAC */
51# define LCD_BPP LCD_COLOR8
wdenk71f95112003-06-15 22:40:42 +000052
53/* you have to set lccr0 and lccr3 (including pcd) */
wdenk8655b6f2004-10-09 23:25:58 +000054# define REG_LCCR0 0x003008f8
55# define REG_LCCR3 0x0300FF01
wdenk71f95112003-06-15 22:40:42 +000056
57/* 640x480x16 @ 61 Hz */
wdenk8655b6f2004-10-09 23:25:58 +000058vidinfo_t panel_info = {
59 vl_col: 640,
60 vl_row: 480,
61 vl_width: 640,
62 vl_height: 480,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 vl_clkp: CONFIG_SYS_HIGH,
64 vl_oep: CONFIG_SYS_HIGH,
65 vl_hsp: CONFIG_SYS_HIGH,
66 vl_vsp: CONFIG_SYS_HIGH,
67 vl_dp: CONFIG_SYS_HIGH,
wdenk8655b6f2004-10-09 23:25:58 +000068 vl_bpix: LCD_BPP,
69 vl_lbw: 0,
70 vl_splt: 0,
71 vl_clor: 0,
72 vl_tft: 1,
73 vl_hpw: 40,
74 vl_blw: 56,
75 vl_elw: 56,
76 vl_vpw: 20,
77 vl_bfw: 8,
78 vl_efw: 8,
wdenk71f95112003-06-15 22:40:42 +000079};
80#endif /* CONFIG_PXA_VIDEO */
81
wdenk8655b6f2004-10-09 23:25:58 +000082/*----------------------------------------------------------------------*/
wdenk71f95112003-06-15 22:40:42 +000083#ifdef CONFIG_SHARP_LM8V31
84
wdenk8655b6f2004-10-09 23:25:58 +000085# define LCD_BPP LCD_COLOR8
86# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
wdenk71f95112003-06-15 22:40:42 +000087
88/* you have to set lccr0 and lccr3 (including pcd) */
wdenk8655b6f2004-10-09 23:25:58 +000089# define REG_LCCR0 0x0030087C
90# define REG_LCCR3 0x0340FF08
wdenk71f95112003-06-15 22:40:42 +000091
wdenk8655b6f2004-10-09 23:25:58 +000092vidinfo_t panel_info = {
93 vl_col: 640,
94 vl_row: 480,
95 vl_width: 157,
96 vl_height: 118,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097 vl_clkp: CONFIG_SYS_HIGH,
98 vl_oep: CONFIG_SYS_HIGH,
99 vl_hsp: CONFIG_SYS_HIGH,
100 vl_vsp: CONFIG_SYS_HIGH,
101 vl_dp: CONFIG_SYS_HIGH,
wdenk8655b6f2004-10-09 23:25:58 +0000102 vl_bpix: LCD_BPP,
103 vl_lbw: 0,
104 vl_splt: 1,
105 vl_clor: 1,
106 vl_tft: 0,
107 vl_hpw: 1,
108 vl_blw: 3,
109 vl_elw: 3,
110 vl_vpw: 1,
111 vl_bfw: 0,
112 vl_efw: 0,
wdenk71f95112003-06-15 22:40:42 +0000113};
114#endif /* CONFIG_SHARP_LM8V31 */
115
116/*----------------------------------------------------------------------*/
wdenk8655b6f2004-10-09 23:25:58 +0000117#ifdef CONFIG_HITACHI_SX14
118/* Hitachi SX14Q004-ZZA color STN LCD */
119#define LCD_BPP LCD_COLOR8
wdenk71f95112003-06-15 22:40:42 +0000120
wdenk8655b6f2004-10-09 23:25:58 +0000121/* you have to set lccr0 and lccr3 (including pcd) */
122#define REG_LCCR0 0x00301079
123#define REG_LCCR3 0x0340FF20
wdenk71f95112003-06-15 22:40:42 +0000124
wdenk8655b6f2004-10-09 23:25:58 +0000125vidinfo_t panel_info = {
126 vl_col: 320,
127 vl_row: 240,
128 vl_width: 167,
129 vl_height: 109,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 vl_clkp: CONFIG_SYS_HIGH,
131 vl_oep: CONFIG_SYS_HIGH,
132 vl_hsp: CONFIG_SYS_HIGH,
133 vl_vsp: CONFIG_SYS_HIGH,
134 vl_dp: CONFIG_SYS_HIGH,
wdenk8655b6f2004-10-09 23:25:58 +0000135 vl_bpix: LCD_BPP,
136 vl_lbw: 1,
137 vl_splt: 0,
138 vl_clor: 1,
139 vl_tft: 0,
140 vl_hpw: 1,
141 vl_blw: 1,
142 vl_elw: 1,
143 vl_vpw: 7,
144 vl_bfw: 0,
145 vl_efw: 0,
wdenk71f95112003-06-15 22:40:42 +0000146};
wdenk8655b6f2004-10-09 23:25:58 +0000147#endif /* CONFIG_HITACHI_SX14 */
wdenk71f95112003-06-15 22:40:42 +0000148
149/*----------------------------------------------------------------------*/
150
wdenk8655b6f2004-10-09 23:25:58 +0000151#if LCD_BPP == LCD_COLOR8
152void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
153#endif
wdenk71f95112003-06-15 22:40:42 +0000154#if LCD_BPP == LCD_MONOCHROME
wdenk8655b6f2004-10-09 23:25:58 +0000155void lcd_initcolregs (void);
wdenk71f95112003-06-15 22:40:42 +0000156#endif
157
wdenk8655b6f2004-10-09 23:25:58 +0000158#ifdef NOT_USED_SO_FAR
159void lcd_disable (void);
160void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
161#endif /* NOT_USED_SO_FAR */
wdenk71f95112003-06-15 22:40:42 +0000162
wdenk8655b6f2004-10-09 23:25:58 +0000163void lcd_ctrl_init (void *lcdbase);
164void lcd_enable (void);
wdenk71f95112003-06-15 22:40:42 +0000165
wdenk8655b6f2004-10-09 23:25:58 +0000166int lcd_line_length;
167int lcd_color_fg;
168int lcd_color_bg;
wdenk71f95112003-06-15 22:40:42 +0000169
wdenk8655b6f2004-10-09 23:25:58 +0000170void *lcd_base; /* Start of framebuffer memory */
171void *lcd_console_address; /* Start of console buffer */
wdenk71f95112003-06-15 22:40:42 +0000172
wdenk8655b6f2004-10-09 23:25:58 +0000173short console_col;
174short console_row;
wdenk71f95112003-06-15 22:40:42 +0000175
wdenk8655b6f2004-10-09 23:25:58 +0000176static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
177static void pxafb_setup_gpio (vidinfo_t *vid);
178static void pxafb_enable_controller (vidinfo_t *vid);
179static int pxafb_init (vidinfo_t *vid);
wdenk71f95112003-06-15 22:40:42 +0000180/************************************************************************/
181
wdenk71f95112003-06-15 22:40:42 +0000182/************************************************************************/
wdenk8655b6f2004-10-09 23:25:58 +0000183/* --------------- PXA chipset specific functions ------------------- */
wdenk71f95112003-06-15 22:40:42 +0000184/************************************************************************/
185
wdenk8655b6f2004-10-09 23:25:58 +0000186void lcd_ctrl_init (void *lcdbase)
wdenk71f95112003-06-15 22:40:42 +0000187{
wdenk8bde7f72003-06-27 21:31:46 +0000188 pxafb_init_mem(lcdbase, &panel_info);
wdenk71f95112003-06-15 22:40:42 +0000189 pxafb_init(&panel_info);
190 pxafb_setup_gpio(&panel_info);
191 pxafb_enable_controller(&panel_info);
192}
193
194/*----------------------------------------------------------------------*/
wdenk8655b6f2004-10-09 23:25:58 +0000195#ifdef NOT_USED_SO_FAR
196void
wdenk71f95112003-06-15 22:40:42 +0000197lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
198{
199}
wdenk8655b6f2004-10-09 23:25:58 +0000200#endif /* NOT_USED_SO_FAR */
wdenk71f95112003-06-15 22:40:42 +0000201
202/*----------------------------------------------------------------------*/
wdenk71f95112003-06-15 22:40:42 +0000203#if LCD_BPP == LCD_COLOR8
wdenk8655b6f2004-10-09 23:25:58 +0000204void
wdenk71f95112003-06-15 22:40:42 +0000205lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
206{
207 struct pxafb_info *fbi = &panel_info.pxa;
208 unsigned short *palette = (unsigned short *)fbi->palette;
209 u_int val;
wdenk8bde7f72003-06-27 21:31:46 +0000210
wdenk71f95112003-06-15 22:40:42 +0000211 if (regno < fbi->palette_size) {
212 val = ((red << 8) & 0xf800);
213 val |= ((green << 4) & 0x07e0);
214 val |= (blue & 0x001f);
215
216#ifdef LCD_INVERT_COLORS
217 palette[regno] = ~val;
218#else
wdenk8655b6f2004-10-09 23:25:58 +0000219 palette[regno] = val;
wdenk71f95112003-06-15 22:40:42 +0000220#endif
221 }
222
223 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
224 regno, &palette[regno],
225 red, green, blue,
226 palette[regno]);
227}
wdenk8655b6f2004-10-09 23:25:58 +0000228#endif /* LCD_COLOR8 */
wdenk71f95112003-06-15 22:40:42 +0000229
230/*----------------------------------------------------------------------*/
wdenk71f95112003-06-15 22:40:42 +0000231#if LCD_BPP == LCD_MONOCHROME
wdenk71f95112003-06-15 22:40:42 +0000232void lcd_initcolregs (void)
233{
wdenk8655b6f2004-10-09 23:25:58 +0000234 struct pxafb_info *fbi = &panel_info.pxa;
235 cmap = (ushort *)fbi->palette;
wdenk71f95112003-06-15 22:40:42 +0000236 ushort regno;
237
238 for (regno = 0; regno < 16; regno++) {
wdenk8655b6f2004-10-09 23:25:58 +0000239 cmap[regno * 2] = 0;
240 cmap[(regno * 2) + 1] = regno & 0x0f;
wdenk71f95112003-06-15 22:40:42 +0000241 }
242}
wdenk8655b6f2004-10-09 23:25:58 +0000243#endif /* LCD_MONOCHROME */
wdenk71f95112003-06-15 22:40:42 +0000244
245/*----------------------------------------------------------------------*/
wdenk8655b6f2004-10-09 23:25:58 +0000246void lcd_enable (void)
wdenk71f95112003-06-15 22:40:42 +0000247{
248}
249
250/*----------------------------------------------------------------------*/
wdenk71f95112003-06-15 22:40:42 +0000251#ifdef NOT_USED_SO_FAR
252static void lcd_disable (void)
253{
254}
wdenk8655b6f2004-10-09 23:25:58 +0000255#endif /* NOT_USED_SO_FAR */
wdenk71f95112003-06-15 22:40:42 +0000256
257/*----------------------------------------------------------------------*/
258
wdenk8655b6f2004-10-09 23:25:58 +0000259/************************************************************************/
260/* ** PXA255 specific routines */
261/************************************************************************/
262
263/*
264 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
265 * descriptors and palette areas.
266 */
267ulong calc_fbsize (void)
wdenk71f95112003-06-15 22:40:42 +0000268{
wdenk8655b6f2004-10-09 23:25:58 +0000269 ulong size;
270 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
wdenk71f95112003-06-15 22:40:42 +0000271
wdenk8655b6f2004-10-09 23:25:58 +0000272 size = line_length * panel_info.vl_row;
273 size += PAGE_SIZE;
wdenk71f95112003-06-15 22:40:42 +0000274
wdenk8655b6f2004-10-09 23:25:58 +0000275 return size;
wdenk71f95112003-06-15 22:40:42 +0000276}
277
wdenk8655b6f2004-10-09 23:25:58 +0000278static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
wdenk71f95112003-06-15 22:40:42 +0000279{
280 u_long palette_mem_size;
281 struct pxafb_info *fbi = &vid->pxa;
282 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
283
284 fbi->screen = (u_long)lcdbase;
285
286 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
287 palette_mem_size = fbi->palette_size * sizeof(u16);
wdenk8655b6f2004-10-09 23:25:58 +0000288
wdenk71f95112003-06-15 22:40:42 +0000289 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
290 /* locate palette and descs at end of page following fb */
wdenk8655b6f2004-10-09 23:25:58 +0000291 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
wdenk71f95112003-06-15 22:40:42 +0000292
293 return 0;
294}
295
wdenk8655b6f2004-10-09 23:25:58 +0000296static void pxafb_setup_gpio (vidinfo_t *vid)
wdenk71f95112003-06-15 22:40:42 +0000297{
298 u_long lccr0;
299
300 /*
301 * setup is based on type of panel supported
302 */
303
304 lccr0 = vid->pxa.reg_lccr0;
305
306 /* 4 bit interface */
307 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
308 {
309 debug("Setting GPIO for 4 bit data\n");
310 /* bits 58-61 */
311 GPDR1 |= (0xf << 26);
312 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
313
314 /* bits 74-77 */
315 GPDR2 |= (0xf << 10);
316 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
317 }
318
319 /* 8 bit interface */
320 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
wdenk8655b6f2004-10-09 23:25:58 +0000321 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
wdenk71f95112003-06-15 22:40:42 +0000322 {
323 debug("Setting GPIO for 8 bit data\n");
324 /* bits 58-65 */
325 GPDR1 |= (0x3f << 26);
326 GPDR2 |= (0x3);
327
328 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
329 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
330
331 /* bits 74-77 */
332 GPDR2 |= (0xf << 10);
333 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
334 }
335
336 /* 16 bit interface */
337 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
338 {
339 debug("Setting GPIO for 16 bit data\n");
340 /* bits 58-77 */
341 GPDR1 |= (0x3f << 26);
342 GPDR2 |= 0x00003fff;
343
344 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
345 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
346 }
347 else
348 {
349 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
350 }
351}
352
wdenk8655b6f2004-10-09 23:25:58 +0000353static void pxafb_enable_controller (vidinfo_t *vid)
wdenk71f95112003-06-15 22:40:42 +0000354{
355 debug("Enabling LCD controller\n");
356
357 /* Sequence from 11.7.10 */
358 LCCR3 = vid->pxa.reg_lccr3;
359 LCCR2 = vid->pxa.reg_lccr2;
360 LCCR1 = vid->pxa.reg_lccr1;
361 LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
362 FDADR0 = vid->pxa.fdadr0;
363 FDADR1 = vid->pxa.fdadr1;
364 LCCR0 |= LCCR0_ENB;
365
366 CKEN |= CKEN16_LCD;
367
368 debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
369 debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
370 debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
371 debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
372 debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
373 debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
374}
375
wdenk8655b6f2004-10-09 23:25:58 +0000376static int pxafb_init (vidinfo_t *vid)
wdenk71f95112003-06-15 22:40:42 +0000377{
378 struct pxafb_info *fbi = &vid->pxa;
379
380 debug("Configuring PXA LCD\n");
381
382 fbi->reg_lccr0 = REG_LCCR0;
383 fbi->reg_lccr3 = REG_LCCR3;
384
385 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
386 vid->vl_col, vid->vl_hpw,
387 vid->vl_blw, vid->vl_elw);
388 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
389 vid->vl_row, vid->vl_vpw,
390 vid->vl_bfw, vid->vl_efw);
391
392 fbi->reg_lccr1 =
393 LCCR1_DisWdth(vid->vl_col) +
394 LCCR1_HorSnchWdth(vid->vl_hpw) +
395 LCCR1_BegLnDel(vid->vl_blw) +
396 LCCR1_EndLnDel(vid->vl_elw);
wdenk8bde7f72003-06-27 21:31:46 +0000397
wdenk71f95112003-06-15 22:40:42 +0000398 fbi->reg_lccr2 =
399 LCCR2_DisHght(vid->vl_row) +
400 LCCR2_VrtSnchWdth(vid->vl_vpw) +
401 LCCR2_BegFrmDel(vid->vl_bfw) +
402 LCCR2_EndFrmDel(vid->vl_efw);
403
wdenk8bde7f72003-06-27 21:31:46 +0000404 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
wdenk8655b6f2004-10-09 23:25:58 +0000405 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
406 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
wdenk8bde7f72003-06-27 21:31:46 +0000407
wdenk71f95112003-06-15 22:40:42 +0000408
409 /* setup dma descriptors */
410 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
411 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
412 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
413
414 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
wdenk8bde7f72003-06-27 21:31:46 +0000415 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
416 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
417
wdenk71f95112003-06-15 22:40:42 +0000418 /* populate descriptors */
419 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
420 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
421 fbi->dmadesc_fblow->fidr = 0;
422 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
423
424 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
wdenk8bde7f72003-06-27 21:31:46 +0000425
wdenk71f95112003-06-15 22:40:42 +0000426 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
427 fbi->dmadesc_fbhigh->fidr = 0;
428 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
429
430 fbi->dmadesc_palette->fsadr = fbi->palette;
431 fbi->dmadesc_palette->fidr = 0;
432 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
433
434 if( NBITS(vid->vl_bpix) < 12)
435 {
436 /* assume any mode with <12 bpp is palette driven */
437 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
438 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
439 /* flips back and forth between pal and fbhigh */
wdenk8bde7f72003-06-27 21:31:46 +0000440 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
wdenk71f95112003-06-15 22:40:42 +0000441 }
442 else
443 {
444 /* palette shouldn't be loaded in true-color mode */
445 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
446 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
447 }
448
449 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
450 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
451 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
452
453 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
454 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
455 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
456
457 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
458 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
459 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
460
461 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
462 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
463 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
wdenk8bde7f72003-06-27 21:31:46 +0000464
wdenk71f95112003-06-15 22:40:42 +0000465 return 0;
466}
467
468/************************************************************************/
469/************************************************************************/
470
471#endif /* CONFIG_LCD */