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wdenk935ecca2002-08-06 20:46:37 +00001#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <linux/config.h>
11
12#include <asm/ptrace.h>
13#include <asm/types.h>
14
15/* Machine State Register (MSR) Fields */
16
17#ifdef CONFIG_PPC64BRIDGE
18#define MSR_SF (1<<63)
19#define MSR_ISF (1<<61)
20#endif /* CONFIG_PPC64BRIDGE */
wdenk42d1f032003-10-15 23:53:47 +000021#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
22#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
23#define MSR_SPE (1<<25) /* Enable SPE(e500) */
wdenk935ecca2002-08-06 20:46:37 +000024#define MSR_POW (1<<18) /* Enable Power Management */
25#define MSR_WE (1<<18) /* Wait State Enable */
26#define MSR_TGPR (1<<17) /* TLB Update registers in use */
27#define MSR_CE (1<<17) /* Critical Interrupt Enable */
28#define MSR_ILE (1<<16) /* Interrupt Little Endian */
29#define MSR_EE (1<<15) /* External Interrupt Enable */
30#define MSR_PR (1<<14) /* Problem State / Privilege Level */
31#define MSR_FP (1<<13) /* Floating Point enable */
32#define MSR_ME (1<<12) /* Machine Check Enable */
33#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34#define MSR_SE (1<<10) /* Single Step */
wdenk42d1f032003-10-15 23:53:47 +000035#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
wdenk935ecca2002-08-06 20:46:37 +000037#define MSR_BE (1<<9) /* Branch Trace */
38#define MSR_DE (1<<9) /* Debug Exception Enable */
39#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
40#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
41#define MSR_IR (1<<5) /* Instruction Relocate */
wdenk42d1f032003-10-15 23:53:47 +000042#define MSR_IS (1<<5) /* Book E Instruction space */
wdenk935ecca2002-08-06 20:46:37 +000043#define MSR_DR (1<<4) /* Data Relocate */
wdenk42d1f032003-10-15 23:53:47 +000044#define MSR_DS (1<<4) /* Book E Data space */
wdenk935ecca2002-08-06 20:46:37 +000045#define MSR_PE (1<<3) /* Protection Enable */
46#define MSR_PX (1<<2) /* Protection Exclusive Mode */
wdenk42d1f032003-10-15 23:53:47 +000047#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
wdenk935ecca2002-08-06 20:46:37 +000048#define MSR_RI (1<<1) /* Recoverable Exception */
49#define MSR_LE (1<<0) /* Little Endian */
50
51#ifdef CONFIG_APUS_FAST_EXCEPT
52#define MSR_ MSR_ME|MSR_IP|MSR_RI
53#else
54#define MSR_ MSR_ME|MSR_RI
55#endif
wdenk42d1f032003-10-15 23:53:47 +000056#ifndef CONFIG_E500
wdenk935ecca2002-08-06 20:46:37 +000057#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
wdenk42d1f032003-10-15 23:53:47 +000058#else
59#define MSR_KERNEL MSR_ME
60#endif
wdenk935ecca2002-08-06 20:46:37 +000061#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
62
63/* Floating Point Status and Control Register (FPSCR) Fields */
64
65#define FPSCR_FX 0x80000000 /* FPU exception summary */
66#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
67#define FPSCR_VX 0x20000000 /* Invalid operation summary */
68#define FPSCR_OX 0x10000000 /* Overflow exception summary */
69#define FPSCR_UX 0x08000000 /* Underflow exception summary */
70#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
71#define FPSCR_XX 0x02000000 /* Inexact exception summary */
72#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
73#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
74#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
75#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
76#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
77#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
78#define FPSCR_FR 0x00040000 /* Fraction rounded */
79#define FPSCR_FI 0x00020000 /* Fraction inexact */
80#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
81#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
82#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
83#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
84#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
85#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
86#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
87#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
88#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
89#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
90#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
91#define FPSCR_RN 0x00000003 /* FPU rounding control */
92
93/* Special Purpose Registers (SPRNs)*/
94
wdenk3c74e322004-02-22 23:46:08 +000095#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
96#define SPRN_CTR 0x009 /* Count Register */
97#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
wdenk42d1f032003-10-15 23:53:47 +000098#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +000099#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
100#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
wdenk42d1f032003-10-15 23:53:47 +0000101#else
102#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
103#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
104#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000105#define SPRN_DAR 0x013 /* Data Address Register */
106#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
107#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
108#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
109#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
110#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
111#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
112#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
113#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
114#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
115#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
116#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
117#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
118#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
119#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
120#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
121#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
122#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
123#define DBCR_EDM 0x80000000
124#define DBCR_IDM 0x40000000
125#define DBCR_RST(x) (((x) & 0x3) << 28)
126#define DBCR_RST_NONE 0
127#define DBCR_RST_CORE 1
128#define DBCR_RST_CHIP 2
129#define DBCR_RST_SYSTEM 3
130#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
131#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
132#define DBCR_EDE 0x02000000 /* Exception Debug Event */
133#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
134#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
135#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
136#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
137#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
138#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
139#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
140#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
141#define DAC_BYTE 0
142#define DAC_HALF 1
143#define DAC_WORD 2
144#define DAC_QUAD 3
145#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
146#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
147#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
148#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
149#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
150#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
151#define DBCR_SIA 0x00000008 /* Second IAC Enable */
152#define DBCR_SDA 0x00000004 /* Second DAC Enable */
153#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
154#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
wdenk42d1f032003-10-15 23:53:47 +0000155#ifndef CONFIG_BOOKE
156#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
157#else
158#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
159#endif /* CONFIG_BOOKE */
160#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000161#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
162#define SPRN_DBSR 0x3F0 /* Debug Status Register */
wdenk42d1f032003-10-15 23:53:47 +0000163#else
164#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
165#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
166#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
167#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
168#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000169#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
170#define DCCR_NOCACHE 0 /* Noncacheable */
171#define DCCR_CACHE 1 /* Cacheable */
172#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
173#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
174#define DCWR_COPY 0 /* Copy-back */
175#define DCWR_WRITE 1 /* Write-through */
wdenk42d1f032003-10-15 23:53:47 +0000176#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000177#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
wdenk42d1f032003-10-15 23:53:47 +0000178#else
179#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
180#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000181#define SPRN_DEC 0x016 /* Decrement Register */
182#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
183#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
184#define SPRN_EAR 0x11A /* External Address Register */
wdenk42d1f032003-10-15 23:53:47 +0000185#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000186#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
wdenk42d1f032003-10-15 23:53:47 +0000187#else
188#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
189#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000190#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
191#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
192#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
193#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
194#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
195#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
196#define ESR_PTR 0x02000000 /* Program Exception - Trap */
197#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
198#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
199#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
200#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
201#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
202#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500203
204#define HID0_ICE_SHIFT 15
205#define HID0_DCE_SHIFT 14
206#define HID0_DLOCK_SHIFT 12
207
wdenk3c74e322004-02-22 23:46:08 +0000208#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
209#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
210#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
211#define HID0_SBCLK (1<<27)
212#define HID0_EICE (1<<26)
213#define HID0_ECLK (1<<25)
214#define HID0_PAR (1<<24)
215#define HID0_DOZE (1<<23)
216#define HID0_NAP (1<<22)
217#define HID0_SLEEP (1<<21)
218#define HID0_DPM (1<<20)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500219#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
220#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
wdenk3c74e322004-02-22 23:46:08 +0000221#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500222#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
wdenk3c74e322004-02-22 23:46:08 +0000223#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
224#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
225#define HID0_DCI HID0_DCFI
wdenk935ecca2002-08-06 20:46:37 +0000226#define HID0_SPD (1<<9) /* Speculative disable */
227#define HID0_SGE (1<<7) /* Store Gathering Enable */
wdenk3c74e322004-02-22 23:46:08 +0000228#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
wdenk935ecca2002-08-06 20:46:37 +0000229#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
230#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
231#define HID0_ABE (1<<3) /* Address Broadcast Enable */
wdenk3c74e322004-02-22 23:46:08 +0000232#define HID0_BHTE (1<<2) /* Branch History Table Enable */
233#define HID0_BTCD (1<<1) /* Branch target cache disable */
234#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
235#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
wdenk42d1f032003-10-15 23:53:47 +0000236#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000237#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
238#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
wdenk42d1f032003-10-15 23:53:47 +0000239#else
240#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
241#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
242#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000243#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
244#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
245#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
246#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
247#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
248#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
249#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
250#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
251#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
252#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
253#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
254#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
255#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
256#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
257#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
258#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
259#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
260#define ICCR_NOCACHE 0 /* Noncacheable */
261#define ICCR_CACHE 1 /* Cacheable */
262#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
263#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
264#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
265#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
266#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
267#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
268#define SPRN_LR 0x008 /* Link Register */
269#define SPRN_MBAR 0x137 /* System memory base address */
270#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
271#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
272#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
273#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
274#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
275#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
wdenk42d1f032003-10-15 23:53:47 +0000276#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000277#define SPRN_PID 0x3B1 /* Process ID */
278#define SPRN_PIR 0x3FF /* Processor Identification Register */
wdenk42d1f032003-10-15 23:53:47 +0000279#else
280#define SPRN_PID 0x030 /* Book E Process ID */
281#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
282#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000283#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
284#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
285#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
286#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
287#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
288#define SPRN_PVR 0x11F /* Processor Version Register */
289#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
290#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
291#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
292#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
293#define SGR_NORMAL 0
294#define SGR_GUARDED 1
295#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
296#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
297#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
298#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
299#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
300#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
301#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
302#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
303#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000304#ifdef CONFIG_BOOKE
305#define SPRN_SVR 0x3FF /* System Version Register */
306#else
307#define SPRN_SVR 0x11E /* System Version Register */
308#endif
wdenk3c74e322004-02-22 23:46:08 +0000309#define SPRN_TBHI 0x3DC /* Time Base High */
310#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
311#define SPRN_TBLO 0x3DD /* Time Base Low */
312#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
313#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
314#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
315#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
316#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
wdenk42d1f032003-10-15 23:53:47 +0000317#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000318#define SPRN_TCR 0x3DA /* Timer Control Register */
wdenk42d1f032003-10-15 23:53:47 +0000319#else
320#define SPRN_TCR 0x154 /* Book E Timer Control Register */
321#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000322#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
323#define WP_2_17 0 /* 2^17 clocks */
324#define WP_2_21 1 /* 2^21 clocks */
325#define WP_2_25 2 /* 2^25 clocks */
326#define WP_2_29 3 /* 2^29 clocks */
327#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
328#define WRC_NONE 0 /* No reset will occur */
329#define WRC_CORE 1 /* Core reset will occur */
330#define WRC_CHIP 2 /* Chip reset will occur */
331#define WRC_SYSTEM 3 /* System reset will occur */
332#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
333#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
334#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
335#define FP_2_9 0 /* 2^9 clocks */
336#define FP_2_13 1 /* 2^13 clocks */
337#define FP_2_17 2 /* 2^17 clocks */
338#define FP_2_21 3 /* 2^21 clocks */
339#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
340#define TCR_ARE 0x00400000 /* Auto Reload Enable */
341#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
342#define THRM1_TIN (1<<0)
343#define THRM1_TIV (1<<1)
344#define THRM1_THRES (0x7f<<2)
345#define THRM1_TID (1<<29)
346#define THRM1_TIE (1<<30)
347#define THRM1_V (1<<31)
348#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
349#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
350#define THRM3_E (1<<31)
wdenk42d1f032003-10-15 23:53:47 +0000351#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
352#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000353#define SPRN_TSR 0x3D8 /* Timer Status Register */
wdenk42d1f032003-10-15 23:53:47 +0000354#else
355#define SPRN_TSR 0x150 /* Book E Timer Status Register */
356#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000357#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
358#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
359#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
360#define WRS_NONE 0 /* No WDT reset occurred */
361#define WRS_CORE 1 /* WDT forced core reset */
362#define WRS_CHIP 2 /* WDT forced chip reset */
363#define WRS_SYSTEM 3 /* WDT forced system reset */
364#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
365#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
366#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
367#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
368#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
369#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
370#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
371#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
372#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
373#define SPRN_XER 0x001 /* Fixed Point Exception Register */
374#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
wdenk935ecca2002-08-06 20:46:37 +0000375
wdenk42d1f032003-10-15 23:53:47 +0000376/* Book E definitions */
377#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
378#define SPRN_CSRR0 0x03A /* Critical SRR0 */
379#define SPRN_CSRR1 0x03B /* Critical SRR0 */
wdenk3c74e322004-02-22 23:46:08 +0000380#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
wdenk42d1f032003-10-15 23:53:47 +0000381#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
wdenk3c74e322004-02-22 23:46:08 +0000382#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
383#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
384#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
385#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
386#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
387#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
388#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
389#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
wdenk42d1f032003-10-15 23:53:47 +0000390#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
wdenk3c74e322004-02-22 23:46:08 +0000391#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
392#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
wdenk42d1f032003-10-15 23:53:47 +0000393#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
394#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
395#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
396#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
397#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
398#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
399#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
400#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
401#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
402#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
403#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
404#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
405#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
406#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
407#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
408#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
409#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
410#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
411
412/* e500 definitions */
413#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
414#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
415#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
416#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
417#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
418#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
419
wdenk3c74e322004-02-22 23:46:08 +0000420#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
wdenk42d1f032003-10-15 23:53:47 +0000421#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
422#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
423#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
424#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
425#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
426#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
427#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500428#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
wdenk42d1f032003-10-15 23:53:47 +0000429
430#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
431#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
432#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
433#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
434#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
435
436#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
437#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
438#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
439#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
440#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
441#define SPRN_PID1 0x279 /* Process ID Register 1 */
442#define SPRN_PID2 0x27a /* Process ID Register 2 */
443#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
444#define ESR_ST 0x00800000 /* Store Operation */
445
wdenk935ecca2002-08-06 20:46:37 +0000446/* Short-hand versions for a number of the above SPRNs */
447
wdenk3c74e322004-02-22 23:46:08 +0000448#define CTR SPRN_CTR /* Counter Register */
449#define DAR SPRN_DAR /* Data Address Register */
450#define DABR SPRN_DABR /* Data Address Breakpoint Register */
451#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
452#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
453#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
454#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
455#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
456#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
457#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
458#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
459#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
460#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
461#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
462#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
463#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
464#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
465#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
466#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
467#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
468#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
469#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
470#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
471#define DBSR SPRN_DBSR /* Debug Status Register */
472#define DCMP SPRN_DCMP /* Data TLB Compare Register */
473#define DEC SPRN_DEC /* Decrement Register */
474#define DMISS SPRN_DMISS /* Data TLB Miss Register */
475#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
476#define EAR SPRN_EAR /* External Address Register */
477#define ESR SPRN_ESR /* Exception Syndrome Register */
478#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
479#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
480#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
481#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
482#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
483#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
484#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
485#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
486#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
487#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
488#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
489#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
490#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
491#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
492#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
493#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
494#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
495#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
496#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
497#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
498#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
499#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
500#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
501#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
502#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
503#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
504#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
505#define LR SPRN_LR
506#define MBAR SPRN_MBAR /* System memory base address */
wdenk42d1f032003-10-15 23:53:47 +0000507#if defined(CONFIG_E500)
508#define PIR SPRN_PIR
509#endif
wdenk36c72872004-06-09 17:45:32 +0000510#define SVR SPRN_SVR /* System-On-Chip Version Register */
wdenk3c74e322004-02-22 23:46:08 +0000511#define PVR SPRN_PVR /* Processor Version */
512#define RPA SPRN_RPA /* Required Physical Address Register */
513#define SDR1 SPRN_SDR1 /* MMU hash base register */
514#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
515#define SPR1 SPRN_SPRG1
516#define SPR2 SPRN_SPRG2
517#define SPR3 SPRN_SPRG3
518#define SPRG0 SPRN_SPRG0
519#define SPRG1 SPRN_SPRG1
520#define SPRG2 SPRN_SPRG2
521#define SPRG3 SPRN_SPRG3
522#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
523#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000524#define SVR SPRN_SVR /* System Version Register */
wdenk3c74e322004-02-22 23:46:08 +0000525#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
526#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
527#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
528#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
529#define TCR SPRN_TCR /* Timer Control Register */
530#define TSR SPRN_TSR /* Timer Status Register */
wdenk935ecca2002-08-06 20:46:37 +0000531#define ICTC 1019
wdenk3c74e322004-02-22 23:46:08 +0000532#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
533#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
534#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
535#define XER SPRN_XER
wdenk935ecca2002-08-06 20:46:37 +0000536
wdenk3c74e322004-02-22 23:46:08 +0000537#define DECAR SPRN_DECAR
538#define CSRR0 SPRN_CSRR0
539#define CSRR1 SPRN_CSRR1
540#define IVPR SPRN_IVPR
541#define USPRG0 SPRN_USPRG0
542#define SPRG4R SPRN_SPRG4R
543#define SPRG5R SPRN_SPRG5R
544#define SPRG6R SPRN_SPRG6R
545#define SPRG7R SPRN_SPRG7R
546#define SPRG4W SPRN_SPRG4W
547#define SPRG5W SPRN_SPRG5W
548#define SPRG6W SPRN_SPRG6W
549#define SPRG7W SPRN_SPRG7W
wdenk42d1f032003-10-15 23:53:47 +0000550#define DEAR SPRN_DEAR
wdenk3c74e322004-02-22 23:46:08 +0000551#define DBCR2 SPRN_DBCR2
552#define IAC3 SPRN_IAC3
553#define IAC4 SPRN_IAC4
554#define DVC1 SPRN_DVC1
555#define DVC2 SPRN_DVC2
556#define IVOR0 SPRN_IVOR0
557#define IVOR1 SPRN_IVOR1
558#define IVOR2 SPRN_IVOR2
559#define IVOR3 SPRN_IVOR3
560#define IVOR4 SPRN_IVOR4
561#define IVOR5 SPRN_IVOR5
562#define IVOR6 SPRN_IVOR6
563#define IVOR7 SPRN_IVOR7
564#define IVOR8 SPRN_IVOR8
565#define IVOR9 SPRN_IVOR9
566#define IVOR10 SPRN_IVOR10
567#define IVOR11 SPRN_IVOR11
568#define IVOR12 SPRN_IVOR12
569#define IVOR13 SPRN_IVOR13
570#define IVOR14 SPRN_IVOR14
571#define IVOR15 SPRN_IVOR15
wdenk42d1f032003-10-15 23:53:47 +0000572#define IVOR32 SPRN_IVOR32
573#define IVOR33 SPRN_IVOR33
574#define IVOR34 SPRN_IVOR34
575#define IVOR35 SPRN_IVOR35
576#define MCSRR0 SPRN_MCSRR0
577#define MCSRR1 SPRN_MCSRR1
578#define L1CSR0 SPRN_L1CSR0
579#define L1CSR1 SPRN_L1CSR1
580#define MCSR SPRN_MCSR
581#define MMUCSR0 SPRN_MMUCSR0
582#define BUCSR SPRN_BUCSR
583#define PID0 SPRN_PID
584#define PID1 SPRN_PID1
585#define PID2 SPRN_PID2
586#define MAS0 SPRN_MAS0
587#define MAS1 SPRN_MAS1
588#define MAS2 SPRN_MAS2
589#define MAS3 SPRN_MAS3
590#define MAS4 SPRN_MAS4
591#define MAS5 SPRN_MAS5
592#define MAS6 SPRN_MAS6
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500593#define MAS7 SPRN_MAS7
wdenk935ecca2002-08-06 20:46:37 +0000594
595/* Device Control Registers */
596
wdenk3c74e322004-02-22 23:46:08 +0000597#define DCRN_BEAR 0x090 /* Bus Error Address Register */
598#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
599#define BESR_DSES 0x80000000 /* Data-Side Error Status */
600#define BESR_DMES 0x40000000 /* DMA Error Status */
601#define BESR_RWS 0x20000000 /* Read/Write Status */
602#define BESR_ETMASK 0x1C000000 /* Error Type */
603#define ET_PROT 0
604#define ET_PARITY 1
605#define ET_NCFG 2
606#define ET_BUSERR 4
607#define ET_BUSTO 6
608#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
609#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
610#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
611#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
612#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
613#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
614#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
615#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
616#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
617#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
618#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
619#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
620#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
621#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
622#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
623#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
624#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
625#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
626#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
627#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
628#define DCRN_DMASR 0x0E0 /* DMA Status Register */
629#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
630#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
631#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
632#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
633#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
634#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
635#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
636#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
637#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
638#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
639#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
640#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
641#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
642#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
643#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
644#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
645#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
646#define IOCR_E0TE 0x80000000
647#define IOCR_E0LP 0x40000000
648#define IOCR_E1TE 0x20000000
649#define IOCR_E1LP 0x10000000
650#define IOCR_E2TE 0x08000000
651#define IOCR_E2LP 0x04000000
652#define IOCR_E3TE 0x02000000
653#define IOCR_E3LP 0x01000000
654#define IOCR_E4TE 0x00800000
655#define IOCR_E4LP 0x00400000
656#define IOCR_EDT 0x00080000
657#define IOCR_SOR 0x00040000
658#define IOCR_EDO 0x00008000
659#define IOCR_2XC 0x00004000
660#define IOCR_ATC 0x00002000
661#define IOCR_SPD 0x00001000
662#define IOCR_BEM 0x00000800
663#define IOCR_PTD 0x00000400
664#define IOCR_ARE 0x00000080
665#define IOCR_DRC 0x00000020
666#define IOCR_RDM(x) (((x) & 0x3) << 3)
667#define IOCR_TCS 0x00000004
668#define IOCR_SCS 0x00000002
669#define IOCR_SPC 0x00000001
wdenk935ecca2002-08-06 20:46:37 +0000670
wdenk36c72872004-06-09 17:45:32 +0000671/* System-On-Chip Version Register */
672
673/* System-On-Chip Version Register (SVR) field extraction */
674
675#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
676#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
677
678#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
679#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
680#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
681#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
682#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
683#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
684#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
685
686/* System-On-Chip Version Numbers (version field only) */
687#define SVR_MPC5200 0x8011
wdenk935ecca2002-08-06 20:46:37 +0000688
689/* Processor Version Register */
690
691/* Processor Version Register (PVR) field extraction */
692
wdenk3c74e322004-02-22 23:46:08 +0000693#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
694#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
wdenk935ecca2002-08-06 20:46:37 +0000695
696/*
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200697 * AMCC has further subdivided the standard PowerPC 16-bit version and
wdenk935ecca2002-08-06 20:46:37 +0000698 * revision subfields of the PVR for the PowerPC 403s into the following:
699 */
700
wdenk3c74e322004-02-22 23:46:08 +0000701#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
702#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
703#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
704#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
705#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
706#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
wdenk935ecca2002-08-06 20:46:37 +0000707
708/* Processor Version Numbers */
709
wdenk3c74e322004-02-22 23:46:08 +0000710#define PVR_403GA 0x00200000
711#define PVR_403GB 0x00200100
712#define PVR_403GC 0x00200200
713#define PVR_403GCX 0x00201400
714#define PVR_405GP 0x40110000
715#define PVR_405GP_RB 0x40110040
716#define PVR_405GP_RC 0x40110082
717#define PVR_405GP_RD 0x401100C4
718#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
719#define PVR_405CR_RA 0x40110041
720#define PVR_405CR_RB 0x401100C5
721#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
722#define PVR_405EP_RA 0x51210950
723#define PVR_405GPR_RB 0x50910951
724#define PVR_440GP_RB 0x40120440
725#define PVR_440GP_RC 0x40120481
Stefan Roesec157d8e2005-08-01 16:41:48 +0200726#define PVR_440EP_RA 0x42221850
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200727#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
728#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
wdenk3c74e322004-02-22 23:46:08 +0000729#define PVR_440GX_RA 0x51B21850
730#define PVR_440GX_RB 0x51B21851
stroese0a7c5392005-04-07 05:33:41 +0000731#define PVR_440GX_RC 0x51B21892
wdenk3c74e322004-02-22 23:46:08 +0000732#define PVR_405EP_RB 0x51210950
733#define PVR_601 0x00010000
734#define PVR_602 0x00050000
735#define PVR_603 0x00030000
736#define PVR_603e 0x00060000
737#define PVR_603ev 0x00070000
738#define PVR_603r 0x00071000
739#define PVR_604 0x00040000
740#define PVR_604e 0x00090000
741#define PVR_604r 0x000A0000
742#define PVR_620 0x00140000
743#define PVR_740 0x00080000
744#define PVR_750 PVR_740
745#define PVR_740P 0x10080000
746#define PVR_750P PVR_740P
wdenk42d1f032003-10-15 23:53:47 +0000747#define PVR_7400 0x000C0000
748#define PVR_7410 0x800C0000
749#define PVR_7450 0x80000000
wdenk0ac6f8b2004-07-09 23:27:13 +0000750
751#define PVR_85xx 0x80200000
752#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
753#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
754
wdenk42d1f032003-10-15 23:53:47 +0000755
wdenk935ecca2002-08-06 20:46:37 +0000756/*
757 * For the 8xx processors, all of them report the same PVR family for
758 * the PowerPC core. The various versions of these processors must be
759 * differentiated by the version number in the Communication Processor
760 * Module (CPM).
761 */
wdenk3c74e322004-02-22 23:46:08 +0000762#define PVR_821 0x00500000
763#define PVR_823 PVR_821
764#define PVR_850 PVR_821
765#define PVR_860 PVR_821
766#define PVR_7400 0x000C0000
767#define PVR_8240 0x00810100
wdenk935ecca2002-08-06 20:46:37 +0000768
wdenk8564acf2003-07-14 22:13:32 +0000769/*
770 * PowerQUICC II family processors report different PVR values depending
771 * on silicon process (HiP3, HiP4, HiP7, etc.)
772 */
773#define PVR_8260 PVR_8240
774#define PVR_8260_HIP3 0x00810101
775#define PVR_8260_HIP4 0x80811014
776#define PVR_8260_HIP7 0x80822011
wdenk5779d8d2003-12-06 23:55:10 +0000777#define PVR_8260_HIP7R1 0x80822013
wdenke1599e82004-10-10 23:27:33 +0000778#define PVR_8260_HIP7RA 0x80822014
wdenk935ecca2002-08-06 20:46:37 +0000779
wdenk0ac6f8b2004-07-09 23:27:13 +0000780
781/*
782 * System Version Register
783 */
784
785/* System Version Register (SVR) field extraction */
786
787#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
788#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
789
790#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
791#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
792
793#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
794#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
795
796
797/*
798 * SVR_VER() Version Values
799 */
800
801#define SVR_8540 0x8030
802#define SVR_8560 0x8070
803#define SVR_8555 0x8079
804#define SVR_8541 0x807A
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500805#define SVR_8548 0x8031
806#define SVR_8548_E 0x8039
wdenk0ac6f8b2004-07-09 23:27:13 +0000807
808
wdenk935ecca2002-08-06 20:46:37 +0000809/* I am just adding a single entry for 8260 boards. I think we may be
810 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
811 * generic 8xx as well. The boards containing these processors are either
812 * identical at the processor level (due to the high integration) or so
813 * wildly different that testing _machine at run time is best replaced by
814 * conditional compilation by board type (found in their respective .h file).
815 * -- Dan
816 */
817#define _MACH_prep 0x00000001
818#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
819#define _MACH_chrp 0x00000004 /* chrp machine */
820#define _MACH_mbx 0x00000008 /* Motorola MBX board */
821#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */
822#define _MACH_fads 0x00000020 /* Motorola FADS board */
823#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */
824#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */
825#define _MACH_yk 0x00000100 /* Motorola Yellowknife */
826#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
827#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
828#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200829#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */
wdenk935ecca2002-08-06 20:46:37 +0000830#define _MACH_8260 0x00002000 /* Generic 8260 */
831#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
832#define _MACH_tqm860 0x00008000 /* TQM860/L */
833#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
wdenk756f5862005-04-03 15:51:42 +0000834#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
wdenk935ecca2002-08-06 20:46:37 +0000835
836
837/* see residual.h for these */
838#define _PREP_Motorola 0x01 /* motorola prep */
839#define _PREP_Firm 0x02 /* firmworks prep */
840#define _PREP_IBM 0x00 /* ibm prep */
841#define _PREP_Bull 0x03 /* bull prep */
842#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */
843
844/*
845 * Radstone board types
846 */
847#define RS_SYS_TYPE_PPC1 0
848#define RS_SYS_TYPE_PPC2 1
849#define RS_SYS_TYPE_PPC1a 2
850#define RS_SYS_TYPE_PPC2a 3
851#define RS_SYS_TYPE_PPC4 4
852#define RS_SYS_TYPE_PPC4a 5
853#define RS_SYS_TYPE_PPC2ep 6
854
855/* these are arbitrary */
856#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
857#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
858
859#define _GLOBAL(n)\
860 .globl n;\
861n:
862
863/* Macros for setting and retrieving special purpose registers */
864
865#define stringify(s) tostring(s)
866#define tostring(s) #s
867
868#define mfdcr(rn) ({unsigned int rval; \
869 asm volatile("mfdcr %0," stringify(rn) \
870 : "=r" (rval)); rval;})
871#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
872
873#define mfmsr() ({unsigned int rval; \
874 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
875#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
876
877#define mfspr(rn) ({unsigned int rval; \
878 asm volatile("mfspr %0," stringify(rn) \
879 : "=r" (rval)); rval;})
880#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
881
882#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
883
884/* Segment Registers */
885
886#define SR0 0
887#define SR1 1
888#define SR2 2
889#define SR3 3
890#define SR4 4
891#define SR5 5
892#define SR6 6
893#define SR7 7
894#define SR8 8
895#define SR9 9
896#define SR10 10
897#define SR11 11
898#define SR12 12
899#define SR13 13
900#define SR14 14
901#define SR15 15
902
903#ifndef __ASSEMBLY__
904#ifndef CONFIG_MACH_SPECIFIC
905extern int _machine;
906extern int have_of;
907#endif /* CONFIG_MACH_SPECIFIC */
908
909/* what kind of prep workstation we are */
910extern int _prep_type;
911/*
912 * This is used to identify the board type from a given PReP board
913 * vendor. Board revision is also made available.
914 */
915extern unsigned char ucSystemType;
916extern unsigned char ucBoardRev;
917extern unsigned char ucBoardRevMaj, ucBoardRevMin;
918
919struct task_struct;
920void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
921void release_thread(struct task_struct *);
922
923/*
924 * Create a new kernel thread.
925 */
926extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
927
928/*
929 * Bus types
930 */
931#define EISA_bus 0
932#define EISA_bus__is_a_macro /* for versions in ksyms.c */
933#define MCA_bus 0
934#define MCA_bus__is_a_macro /* for versions in ksyms.c */
935
936/* Lazy FPU handling on uni-processor */
937extern struct task_struct *last_task_used_math;
938extern struct task_struct *last_task_used_altivec;
939
940/*
941 * this is the minimum allowable io space due to the location
942 * of the io areas on prep (first one at 0x80000000) but
943 * as soon as I get around to remapping the io areas with the BATs
944 * to match the mac we can raise this. -- Cort
945 */
946#define TASK_SIZE (0x80000000UL)
947
948/* This decides where the kernel will search for a free chunk of vm
949 * space during mmap's.
950 */
951#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
952
953typedef struct {
954 unsigned long seg;
955} mm_segment_t;
956
957struct thread_struct {
958 unsigned long ksp; /* Kernel stack pointer */
959 unsigned long wchan; /* Event task is sleeping on */
960 struct pt_regs *regs; /* Pointer to saved register state */
961 mm_segment_t fs; /* for get_fs() validation */
962 void *pgdir; /* root of page-table tree */
963 signed long last_syscall;
964 double fpr[32]; /* Complete floating point set */
965 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
966 unsigned long fpscr; /* Floating point status */
967#ifdef CONFIG_ALTIVEC
968 vector128 vr[32]; /* Complete AltiVec set */
969 vector128 vscr; /* AltiVec status */
970 unsigned long vrsave;
971#endif /* CONFIG_ALTIVEC */
972};
973
974#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
975
976#define INIT_THREAD { \
977 INIT_SP, /* ksp */ \
978 0, /* wchan */ \
979 (struct pt_regs *)INIT_SP - 1, /* regs */ \
980 KERNEL_DS, /*fs*/ \
981 swapper_pg_dir, /* pgdir */ \
982 0, /* last_syscall */ \
983 {0}, 0, 0 \
984}
985
986/*
987 * Note: the vm_start and vm_end fields here should *not*
988 * be in kernel space. (Could vm_end == vm_start perhaps?)
989 */
990#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
991 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
992 1, NULL, NULL }
993
994/*
995 * Return saved PC of a blocked thread. For now, this is the "user" PC
996 */
997static inline unsigned long thread_saved_pc(struct thread_struct *t)
998{
999 return (t->regs) ? t->regs->nip : 0;
1000}
1001
1002#define copy_segments(tsk, mm) do { } while (0)
1003#define release_segments(mm) do { } while (0)
1004#define forget_segments() do { } while (0)
1005
1006unsigned long get_wchan(struct task_struct *p);
1007
1008#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1009#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1010
1011/*
1012 * NOTE! The task struct and the stack go together
1013 */
1014#define THREAD_SIZE (2*PAGE_SIZE)
1015#define alloc_task_struct() \
1016 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1017#define free_task_struct(p) free_pages((unsigned long)(p),1)
1018#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1019
1020/* in process.c - for early bootup debug -- Cort */
1021int ll_printk(const char *, ...);
1022void ll_puts(const char *);
1023
1024#define init_task (init_task_union.task)
1025#define init_stack (init_task_union.stack)
1026
1027/* In misc.c */
1028void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1029
1030#endif /* ndef ASSEMBLY*/
1031
1032#ifdef CONFIG_MACH_SPECIFIC
1033#if defined(CONFIG_8xx)
1034#define _machine _MACH_8xx
1035#define have_of 0
1036#elif defined(CONFIG_OAK)
1037#define _machine _MACH_oak
1038#define have_of 0
1039#elif defined(CONFIG_WALNUT)
1040#define _machine _MACH_walnut
1041#define have_of 0
1042#elif defined(CONFIG_APUS)
1043#define _machine _MACH_apus
1044#define have_of 0
1045#elif defined(CONFIG_GEMINI)
1046#define _machine _MACH_gemini
1047#define have_of 0
1048#elif defined(CONFIG_8260)
1049#define _machine _MACH_8260
1050#define have_of 0
1051#elif defined(CONFIG_SANDPOINT)
1052#define _machine _MACH_sandpoint
wdenk756f5862005-04-03 15:51:42 +00001053#elif defined(CONFIG_HIDDEN_DRAGON)
1054#define _machine _MACH_hidden_dragon
wdenk935ecca2002-08-06 20:46:37 +00001055#define have_of 0
1056#else
1057#error "Machine not defined correctly"
1058#endif
1059#endif /* CONFIG_MACH_SPECIFIC */
1060
1061#endif /* __ASM_PPC_PROCESSOR_H */