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Michael Trimarchi6b924872008-11-28 13:22:09 +01001/*
Vivek Mahajan4ef01012009-05-25 17:23:16 +05302 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
Michael Trimarchi6b924872008-11-28 13:22:09 +01003 * Copyright (c) 2005 MontaVista Software
4 * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michael Trimarchi6b924872008-11-28 13:22:09 +01007 */
8
Mateusz Kulikowskie162c6b2016-03-31 23:12:23 +02009#ifndef _EHCI_CI_H
10#define _EHCI_CI_H
Michael Trimarchi6b924872008-11-28 13:22:09 +010011
Vivek Mahajan4ef01012009-05-25 17:23:16 +053012#include <asm/processor.h>
13
Nikhil Badola15231f62014-05-08 17:05:26 +053014#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
15
Michael Trimarchi6b924872008-11-28 13:22:09 +010016/* Global offsets */
17#define FSL_SKIP_PCI 0x100
18
19/* offsets for the non-ehci registers in the FSL SOC USB controller */
20#define FSL_SOC_USB_ULPIVP 0x170
21#define FSL_SOC_USB_PORTSC1 0x184
22#define PORT_PTS_MSK (3 << 30)
23#define PORT_PTS_UTMI (0 << 30)
24#define PORT_PTS_ULPI (2 << 30)
25#define PORT_PTS_SERIAL (3 << 30)
26#define PORT_PTS_PTW (1 << 28)
Damien Dusha29c6fbe2010-10-14 15:27:06 +020027#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
28#define PORT_PTS_PHCD (1 << 23)
29#define PORT_PP (1 << 12)
30#define PORT_PR (1 << 8)
Michael Trimarchi6b924872008-11-28 13:22:09 +010031
32/* USBMODE Register bits */
33#define CM_IDLE (0 << 0)
34#define CM_RESERVED (1 << 0)
35#define CM_DEVICE (2 << 0)
36#define CM_HOST (3 << 0)
Damien Dusha29c6fbe2010-10-14 15:27:06 +020037#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
Michael Trimarchi6b924872008-11-28 13:22:09 +010038#define USBMODE_RESERVED_2 (0 << 2)
39#define SLOM (1 << 3)
40#define SDIS (1 << 4)
41
42/* CONTROL Register bits */
43#define ULPI_INT_EN (1 << 0)
44#define WU_INT_EN (1 << 1)
45#define USB_EN (1 << 2)
46#define LSF_EN (1 << 3)
47#define KEEP_OTG_ON (1 << 4)
48#define OTG_PORT (1 << 5)
49#define REFSEL_12MHZ (0 << 6)
50#define REFSEL_16MHZ (1 << 6)
51#define REFSEL_48MHZ (2 << 6)
52#define PLL_RESET (1 << 8)
53#define UTMI_PHY_EN (1 << 9)
54#define PHY_CLK_SEL_UTMI (0 << 10)
55#define PHY_CLK_SEL_ULPI (1 << 10)
56#define CLKIN_SEL_USB_CLK (0 << 11)
57#define CLKIN_SEL_USB_CLK2 (1 << 11)
58#define CLKIN_SEL_SYS_CLK (2 << 11)
59#define CLKIN_SEL_SYS_CLK2 (3 << 11)
60#define RESERVED_18 (0 << 13)
61#define RESERVED_17 (0 << 14)
62#define RESERVED_16 (0 << 15)
63#define WU_INT (1 << 16)
64#define PHY_CLK_VALID (1 << 17)
65
66#define FSL_SOC_USB_PORTSC2 0x188
Damien Dusha29c6fbe2010-10-14 15:27:06 +020067
68/* OTG Status Control Register bits */
69#define FSL_SOC_USB_OTGSC 0x1a4
70#define CTRL_VBUS_DISCHARGE (0x1<<0)
71#define CTRL_VBUS_CHARGE (0x1<<1)
72#define CTRL_OTG_TERMINATION (0x1<<3)
73#define CTRL_DATA_PULSING (0x1<<4)
74#define CTRL_ID_PULL_EN (0x1<<5)
75#define HA_DATA_PULSE (0x1<<6)
76#define HA_BA (0x1<<7)
77#define STS_USB_ID (0x1<<8)
78#define STS_A_VBUS_VALID (0x1<<9)
79#define STS_A_SESSION_VALID (0x1<<10)
80#define STS_B_SESSION_VALID (0x1<<11)
81#define STS_B_SESSION_END (0x1<<12)
82#define STS_1MS_TOGGLE (0x1<<13)
83#define STS_DATA_PULSING (0x1<<14)
84#define INTSTS_USB_ID (0x1<<16)
85#define INTSTS_A_VBUS_VALID (0x1<<17)
86#define INTSTS_A_SESSION_VALID (0x1<<18)
87#define INTSTS_B_SESSION_VALID (0x1<<19)
88#define INTSTS_B_SESSION_END (0x1<<20)
89#define INTSTS_1MS (0x1<<21)
90#define INTSTS_DATA_PULSING (0x1<<22)
91#define INTR_USB_ID_EN (0x1<<24)
92#define INTR_A_VBUS_VALID_EN (0x1<<25)
93#define INTR_A_SESSION_VALID_EN (0x1<<26)
94#define INTR_B_SESSION_VALID_EN (0x1<<27)
95#define INTR_B_SESSION_END_EN (0x1<<28)
96#define INTR_1MS_TIMER_EN (0x1<<29)
97#define INTR_DATA_PULSING_EN (0x1<<30)
98#define INTSTS_MASK (0x00ff0000)
99
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200100#define INTERRUPT_ENABLE_BITS_MASK \
101 (INTR_USB_ID_EN | \
102 INTR_1MS_TIMER_EN | \
103 INTR_A_VBUS_VALID_EN | \
104 INTR_A_SESSION_VALID_EN | \
105 INTR_B_SESSION_VALID_EN | \
106 INTR_B_SESSION_END_EN | \
107 INTR_DATA_PULSING_EN)
108
109#define INTERRUPT_STATUS_BITS_MASK \
110 (INTSTS_USB_ID | \
111 INTR_1MS_TIMER_EN | \
112 INTSTS_A_VBUS_VALID | \
113 INTSTS_A_SESSION_VALID | \
114 INTSTS_B_SESSION_VALID | \
115 INTSTS_B_SESSION_END | \
116 INTSTS_DATA_PULSING)
117
Michael Trimarchi6b924872008-11-28 13:22:09 +0100118#define FSL_SOC_USB_USBMODE 0x1a8
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200119
120#define USBGENCTRL 0x200 /* NOTE: big endian */
121#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
122#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
123#define GC_PPP (1 << 3) /* Port Power Polarity */
124#define GC_PFP (1 << 2) /* Power Fault Polarity */
125#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
126#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
127
128#define ISIPHYCTRL 0x204 /* NOTE: big endian */
129#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
130#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
131#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
132#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
133#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
134
Michael Trimarchi6b924872008-11-28 13:22:09 +0100135#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
136#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
137#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
138#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
139#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
140#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
141#define SNOOP_SIZE_2GB 0x1e
142
143/* System Clock Control Register */
144#define MPC83XX_SCCR_USB_MASK 0x00f00000
145#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
146#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
147#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
148
Anatolij Gustschinfff6ec32010-10-21 18:30:35 +0200149#if defined(CONFIG_MPC83xx)
ramneek mehresh77354e92013-09-12 16:35:49 +0530150#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
151#if defined(CONFIG_MPC834x)
152#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
153#else
154#define CONFIG_SYS_FSL_USB2_ADDR 0
155#endif
Vivek Mahajana07bf182009-05-21 17:32:48 +0530156#elif defined(CONFIG_MPC85xx)
ramneek mehresh77354e92013-09-12 16:35:49 +0530157#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
158#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200159#elif defined(CONFIG_MPC512X)
ramneek mehresh77354e92013-09-12 16:35:49 +0530160#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
161#define CONFIG_SYS_FSL_USB2_ADDR 0
York Sun73fb5832017-03-27 11:41:03 -0700162#elif defined(CONFIG_ARCH_LS1021A)
Rajesh Bhagat9729dc92016-06-07 18:59:34 +0530163#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
Nikhil Badola3f041f02014-10-17 11:35:46 +0530164#define CONFIG_SYS_FSL_USB2_ADDR 0
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530165#endif
166
167/*
Nikhil Badola896720c2014-04-07 08:46:14 +0530168 * Increasing TX FIFO threshold value from 2 to 4 decreases
169 * data burst rate with which data packets are posted from the TX
170 * latency FIFO to compensate for latencies in DDR pipeline during DMA
171 */
172#define TXFIFOTHRESH 4
173
174/*
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530175 * USB Registers
176 */
177struct usb_ehci {
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200178 u32 id; /* 0x000 - Identification register */
179 u32 hwgeneral; /* 0x004 - General hardware parameters */
180 u32 hwhost; /* 0x008 - Host hardware parameters */
181 u32 hwdevice; /* 0x00C - Device hardware parameters */
182 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
183 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
184 u8 res1[0x68];
185 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
186 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
187 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
188 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
189 u32 sbuscfg; /* 0x090 - System Bus Interface Control */
Mateusz Kulikowskid424efb2016-03-31 23:12:24 +0200190 u32 sbusstatus; /* 0x094 - System Bus Interface Status */
191 u32 sbusmode; /* 0x098 - System Bus Interface Mode */
192 u32 genconfig; /* 0x09C - USB Core Configuration */
193 u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
194 u8 res2[0x5c];
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200195 u8 caplength; /* 0x100 - Capability Register Length */
196 u8 res3[0x1];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530197 u16 hciversion; /* 0x102 - Host Interface Version */
198 u32 hcsparams; /* 0x104 - Host Structural Parameters */
199 u32 hccparams; /* 0x108 - Host Capability Parameters */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200200 u8 res4[0x14];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530201 u32 dciversion; /* 0x120 - Device Interface Version */
202 u32 dciparams; /* 0x124 - Device Controller Params */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200203 u8 res5[0x18];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530204 u32 usbcmd; /* 0x140 - USB Command */
205 u32 usbsts; /* 0x144 - USB Status */
206 u32 usbintr; /* 0x148 - USB Interrupt Enable */
207 u32 frindex; /* 0x14C - USB Frame Index */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200208 u8 res6[0x4];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530209 u32 perlistbase; /* 0x154 - Periodic List Base
210 - USB Device Address */
211 u32 ep_list_addr; /* 0x158 - Next Asynchronous List
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200212 - End Point Address */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200213 u8 res7[0x4];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530214 u32 burstsize; /* 0x160 - Programmable Burst Size */
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200215#define FSL_EHCI_TXPBURST(X) ((X) << 8)
216#define FSL_EHCI_RXPBURST(X) (X)
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530217 u32 txfilltuning; /* 0x164 - Host TT Transmit
218 pre-buffer packet tuning */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200219 u8 res8[0x8];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530220 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200221 u8 res9[0xc];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530222 u32 config_flag; /* 0x180 - Configured Flag Register */
223 u32 portsc; /* 0x184 - Port status/control */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200224 u8 res10[0x1C];
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200225 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530226 u32 usbmode; /* 0x1a8 - USB Device Mode */
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200227 u32 epsetupstat; /* 0x1ac - End Point Setup Status */
228 u32 epprime; /* 0x1b0 - End Point Init Status */
229 u32 epflush; /* 0x1b4 - End Point De-initlialize */
230 u32 epstatus; /* 0x1b8 - End Point Status */
231 u32 epcomplete; /* 0x1bc - End Point Complete */
232 u32 epctrl0; /* 0x1c0 - End Point Control 0 */
233 u32 epctrl1; /* 0x1c4 - End Point Control 1 */
234 u32 epctrl2; /* 0x1c8 - End Point Control 2 */
235 u32 epctrl3; /* 0x1cc - End Point Control 3 */
236 u32 epctrl4; /* 0x1d0 - End Point Control 4 */
237 u32 epctrl5; /* 0x1d4 - End Point Control 5 */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200238 u8 res11[0x28];
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200239 u32 usbgenctrl; /* 0x200 - USB General Control */
240 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200241 u8 res12[0x1F8];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530242 u32 snoop1; /* 0x400 - Snoop 1 */
243 u32 snoop2; /* 0x404 - Snoop 2 */
244 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
245 u32 prictrl; /* 0x40c - Priority Control */
246 u32 sictrl; /* 0x410 - System Interface Control */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200247 u8 res13[0xEC];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530248 u32 control; /* 0x500 - Control */
Wolfgang Grandegger0255f2d2011-10-17 20:16:09 +0200249 u8 res14[0xafc];
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530250};
251
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100252/*
253 * For MXC SOCs
254 */
Benoît Thébaudeau8eeb19b2012-11-13 09:55:30 +0000255
256/* values for portsc field */
257#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
258#define MXC_EHCI_FORCE_FS (1 << 24)
259#define MXC_EHCI_UTMI_8BIT (0 << 28)
260#define MXC_EHCI_UTMI_16BIT (1 << 28)
261#define MXC_EHCI_SERIAL (1 << 29)
262#define MXC_EHCI_MODE_UTMI (0 << 30)
263#define MXC_EHCI_MODE_PHILIPS (1 << 30)
264#define MXC_EHCI_MODE_ULPI (2 << 30)
265#define MXC_EHCI_MODE_SERIAL (3 << 30)
266
267/* values for flags field */
268#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
269#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
270#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
271#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
272#define MXC_EHCI_INTERFACE_MASK (0xf)
273
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100274#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000275#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
276#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
277#define MXC_EHCI_TTL_ENABLED (1 << 8)
Benoît Thébaudeau8eeb19b2012-11-13 09:55:30 +0000278
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000279#define MXC_EHCI_INTERNAL_PHY (1 << 9)
280#define MXC_EHCI_IPPUE_DOWN (1 << 10)
281#define MXC_EHCI_IPPUE_UP (1 << 11)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100282
Peng Fan229dbba2014-11-10 08:50:39 +0800283int usb_phy_mode(int port);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100284/* Board-specific initialization */
285int board_ehci_hcd_init(int port);
Peng Fan229dbba2014-11-10 08:50:39 +0800286int board_usb_phy_mode(int port);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100287
Mateusz Kulikowskie162c6b2016-03-31 23:12:23 +0200288#endif /* _EHCI_CI_H */