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Stefan Roesedd580802014-10-22 12:13:18 +02001/*
Stefan Roesec4be10b2015-12-03 12:39:45 +01002 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roesedd580802014-10-22 12:13:18 +02003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_MV7846MP_GP_H
8#define _CONFIG_DB_MV7846MP_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
Stefan Roese25541672015-01-19 11:33:46 +010013#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
14
Stefan Roesedd580802014-10-22 12:13:18 +020015#define CONFIG_DISPLAY_BOARDINFO_LATE
16
Stefan Roese2923c2d2015-08-06 14:27:36 +020017/*
18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
19 * for DDR ECC byte filling in the SPL before loading the main
20 * U-Boot into it.
21 */
22#define CONFIG_SYS_TEXT_BASE 0x00800000
Stefan Roesedd580802014-10-22 12:13:18 +020023#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24
25/*
26 * Commands configuration
27 */
28#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
Stefan Roeseaf2728a2015-12-03 12:39:45 +010029#define CONFIG_CMD_CACHE
Stefan Roesedd580802014-10-22 12:13:18 +020030#define CONFIG_CMD_DHCP
31#define CONFIG_CMD_ENV
Stefan Roese8c822822015-12-03 12:39:45 +010032#define CONFIG_CMD_EXT2
33#define CONFIG_CMD_EXT4
34#define CONFIG_CMD_FAT
35#define CONFIG_CMD_FS_GENERIC
Stefan Roesedd580802014-10-22 12:13:18 +020036#define CONFIG_CMD_I2C
Stefan Roesed6b63032015-07-23 10:26:18 +020037#define CONFIG_CMD_NAND
Stefan Roese41e705a2015-08-11 09:36:15 +020038#define CONFIG_CMD_PCI
Stefan Roesedd580802014-10-22 12:13:18 +020039#define CONFIG_CMD_PING
Stefan Roesec4be10b2015-12-03 12:39:45 +010040#define CONFIG_CMD_SATA
Stefan Roesedd580802014-10-22 12:13:18 +020041#define CONFIG_CMD_SF
42#define CONFIG_CMD_SPI
43#define CONFIG_CMD_TFTPPUT
44#define CONFIG_CMD_TIME
45
46/* I2C */
47#define CONFIG_SYS_I2C
48#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020049#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesedd580802014-10-22 12:13:18 +020050#define CONFIG_SYS_I2C_SLAVE 0x0
51#define CONFIG_SYS_I2C_SPEED 100000
52
Stefan Roese49114c82015-07-22 18:05:43 +020053/* USB/EHCI configuration */
Stefan Roese49114c82015-07-22 18:05:43 +020054#define CONFIG_EHCI_IS_TDI
Anton Schubert8a333712015-07-23 15:02:09 +020055#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Stefan Roese49114c82015-07-22 18:05:43 +020056
Stefan Roesedd580802014-10-22 12:13:18 +020057/* SPI NOR flash default params, used by sf commands */
58#define CONFIG_SF_DEFAULT_SPEED 1000000
59#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roesedd580802014-10-22 12:13:18 +020060
61/* Environment in SPI NOR flash */
62#define CONFIG_ENV_IS_IN_SPI_FLASH
63#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
64#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
65#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
66
67#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roesedd580802014-10-22 12:13:18 +020068#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roesedd580802014-10-22 12:13:18 +020069
70#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
71#define CONFIG_SYS_ALT_MEMTEST
72
Anton Schuberte863f7f2015-07-15 14:50:05 +020073/* SATA support */
Stefan Roesec4be10b2015-12-03 12:39:45 +010074#define CONFIG_SYS_SATA_MAX_DEVICE 2
75#define CONFIG_SATA_MV
76#define CONFIG_LIBATA
77#define CONFIG_LBA48
78#define CONFIG_EFI_PARTITION
Anton Schuberte863f7f2015-07-15 14:50:05 +020079#define CONFIG_DOS_PARTITION
Anton Schuberte863f7f2015-07-15 14:50:05 +020080
Stefan Roese8c822822015-12-03 12:39:45 +010081/* Additional FS support/configuration */
82#define CONFIG_SUPPORT_VFAT
83
Stefan Roese41e705a2015-08-11 09:36:15 +020084/* PCIe support */
Stefan Roese64512232015-11-25 07:37:00 +010085#ifndef CONFIG_SPL_BUILD
Stefan Roese41e705a2015-08-11 09:36:15 +020086#define CONFIG_PCI
87#define CONFIG_PCI_MVEBU
88#define CONFIG_PCI_PNP
89#define CONFIG_PCI_SCAN_SHOW
Stefan Roese64512232015-11-25 07:37:00 +010090#endif
Stefan Roese41e705a2015-08-11 09:36:15 +020091
Stefan Roesed6b63032015-07-23 10:26:18 +020092/* NAND */
93#define CONFIG_SYS_NAND_USE_FLASH_BBT
94#define CONFIG_SYS_NAND_ONFI_DETECTION
95
Stefan Roesedd580802014-10-22 12:13:18 +020096/*
97 * mv-common.h should be defined after CMD configs since it used them
98 * to enable certain macros
99 */
100#include "mv-common.h"
101
Stefan Roese25541672015-01-19 11:33:46 +0100102/*
103 * Memory layout while starting into the bin_hdr via the
104 * BootROM:
105 *
106 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
107 * 0x4000.4030 bin_hdr start address
108 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
109 * 0x4007.fffc BootROM stack top
110 *
111 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
112 * L2 cache thus cannot be used.
113 */
114
115/* SPL */
116/* Defines for SPL */
117#define CONFIG_SPL_FRAMEWORK
118#define CONFIG_SPL_TEXT_BASE 0x40004030
119#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
120
121#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
122#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
123
Stefan Roese64512232015-11-25 07:37:00 +0100124#ifdef CONFIG_SPL_BUILD
125#define CONFIG_SYS_MALLOC_SIMPLE
126#endif
Stefan Roese25541672015-01-19 11:33:46 +0100127
128#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
129#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
130
131#define CONFIG_SPL_LIBCOMMON_SUPPORT
132#define CONFIG_SPL_LIBGENERIC_SUPPORT
133#define CONFIG_SPL_SERIAL_SUPPORT
134#define CONFIG_SPL_I2C_SUPPORT
Stefan Roese25541672015-01-19 11:33:46 +0100135
136/* SPL related SPI defines */
137#define CONFIG_SPL_SPI_SUPPORT
138#define CONFIG_SPL_SPI_FLASH_SUPPORT
139#define CONFIG_SPL_SPI_LOAD
140#define CONFIG_SPL_SPI_BUS 0
141#define CONFIG_SPL_SPI_CS 0
142#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
Stefan Roese2bd87112015-08-03 12:13:09 +0200143#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
Stefan Roese25541672015-01-19 11:33:46 +0100144
145/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roese25541672015-01-19 11:33:46 +0100146#define CONFIG_SPD_EEPROM 0x4e
Stefan Roese698ffab2015-12-10 15:02:38 +0100147#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roese25541672015-01-19 11:33:46 +0100148
Stefan Roesedd580802014-10-22 12:13:18 +0200149#endif /* _CONFIG_DB_MV7846MP_GP_H */