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John Rigby5f91db72008-02-26 09:38:14 -07001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
Wolfgang Denk843efb12009-05-16 10:47:43 +02003 * Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
John Rigby5f91db72008-02-26 09:38:14 -07004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
Wolfgang Denk843efb12009-05-16 10:47:43 +020026#include <asm/io.h>
John Rigby5f91db72008-02-26 09:38:14 -070027#include <asm/mmu.h>
28#include <asm/global_data.h>
29#include <pci.h>
30#if defined(CONFIG_OF_LIBFDT)
31#include <libfdt.h>
32#include <fdt_support.h>
33#endif
34
35DECLARE_GLOBAL_DATA_PTR;
36
37/* System RAM mapped to PCI space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
39#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
John Rigby5f91db72008-02-26 09:38:14 -070040
41static struct pci_controller pci_hose;
42
43
44/**************************************************************************
45 * pci_init_board()
46 *
47 */
48void
49pci_init_board(void)
50{
Wolfgang Denk843efb12009-05-16 10:47:43 +020051 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
John Rigby5f91db72008-02-26 09:38:14 -070052 volatile law512x_t *pci_law;
53 volatile pot512x_t *pci_pot;
54 volatile pcictrl512x_t *pci_ctrl;
55 volatile pciconf512x_t *pci_conf;
56 u16 reg16;
57 u32 reg32;
58 u32 dev;
Wolfgang Denk8b251262009-05-16 10:47:39 +020059 int i;
John Rigby5f91db72008-02-26 09:38:14 -070060 struct pci_controller *hose;
61
62 /* Set PCI divider for 33MHz */
Wolfgang Denk843efb12009-05-16 10:47:43 +020063 reg32 = im->clk.scfr[0];
John Rigby5f91db72008-02-26 09:38:14 -070064 reg32 &= ~(SCFR1_PCI_DIV_MASK);
65 reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
Wolfgang Denk843efb12009-05-16 10:47:43 +020066 im->clk.scfr[0] = reg32;
John Rigby5f91db72008-02-26 09:38:14 -070067
Wolfgang Denk843efb12009-05-16 10:47:43 +020068 clrsetbits_be32(&im->clk.scfr[0],
69 SCFR1_PCI_DIV_MASK,
70 SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
71 );
72
73 pci_law = im->sysconf.pcilaw;
74 pci_pot = im->ios.pot;
75 pci_ctrl = &im->pci_ctrl;
76 pci_conf = &im->pci_conf;
John Rigby5f91db72008-02-26 09:38:14 -070077
78 hose = &pci_hose;
79
80 /*
81 * Release PCI RST Output signal
82 */
Wolfgang Denk843efb12009-05-16 10:47:43 +020083 out_be32(&pci_ctrl->gcr, 0);
John Rigby5f91db72008-02-26 09:38:14 -070084 udelay(2000);
Wolfgang Denk843efb12009-05-16 10:47:43 +020085 out_be32(&pci_ctrl->gcr, 1);
John Rigby5f91db72008-02-26 09:38:14 -070086
87 /* We need to wait at least a 1sec based on PCI specs */
Wolfgang Denk8b251262009-05-16 10:47:39 +020088 for (i = 0; i < 1000; i++)
89 udelay(1000);
John Rigby5f91db72008-02-26 09:38:14 -070090
91 /*
92 * Configure PCI Local Access Windows
93 */
Wolfgang Denk843efb12009-05-16 10:47:43 +020094 out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
95 out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
John Rigby5f91db72008-02-26 09:38:14 -070096
Wolfgang Denk843efb12009-05-16 10:47:43 +020097 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
98 out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
John Rigby5f91db72008-02-26 09:38:14 -070099
100 /*
101 * Configure PCI Outbound Translation Windows
102 */
103
104 /* PCI mem space - prefetch */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200105 out_be32(&pci_pot[0].potar,
106 (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
107 out_be32(&pci_pot[0].pobar,
108 (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
109 out_be32(&pci_pot[0].pocmr,
110 POCMR_EN | POCMR_PRE | POCMR_CM_256M);
John Rigby5f91db72008-02-26 09:38:14 -0700111
112 /* PCI IO space */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200113 out_be32(&pci_pot[1].potar,
114 (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
115 out_be32(&pci_pot[1].pobar,
116 (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
117 out_be32(&pci_pot[1].pocmr,
118 POCMR_EN | POCMR_IO | POCMR_CM_16M);
John Rigby5f91db72008-02-26 09:38:14 -0700119
120 /* PCI mmio - non-prefetch mem space */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200121 out_be32(&pci_pot[2].potar,
122 (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
123 out_be32(&pci_pot[2].pobar,
124 (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
125 out_be32(&pci_pot[2].pocmr,
126 POCMR_EN | POCMR_CM_256M);
John Rigby5f91db72008-02-26 09:38:14 -0700127
128 /*
129 * Configure PCI Inbound Translation Windows
130 */
131
132 /* we need RAM mapped to PCI space for the devices to
133 * access main memory */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200134 out_be32(&pci_ctrl[0].pitar1, 0x0);
135 out_be32(&pci_ctrl[0].pibar1, 0x0);
136 out_be32(&pci_ctrl[0].piebar1, 0x0);
137 out_be32(&pci_ctrl[0].piwar1,
138 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
139 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
John Rigby5f91db72008-02-26 09:38:14 -0700140
141 hose->first_busno = 0;
142 hose->last_busno = 0xff;
143
144 /* PCI memory prefetch space */
145 pci_set_region(hose->regions + 0,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 CONFIG_SYS_PCI_MEM_BASE,
147 CONFIG_SYS_PCI_MEM_PHYS,
148 CONFIG_SYS_PCI_MEM_SIZE,
John Rigby5f91db72008-02-26 09:38:14 -0700149 PCI_REGION_MEM|PCI_REGION_PREFETCH);
150
151 /* PCI memory space */
152 pci_set_region(hose->regions + 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 CONFIG_SYS_PCI_MMIO_BASE,
154 CONFIG_SYS_PCI_MMIO_PHYS,
155 CONFIG_SYS_PCI_MMIO_SIZE,
John Rigby5f91db72008-02-26 09:38:14 -0700156 PCI_REGION_MEM);
157
158 /* PCI IO space */
159 pci_set_region(hose->regions + 2,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 CONFIG_SYS_PCI_IO_BASE,
161 CONFIG_SYS_PCI_IO_PHYS,
162 CONFIG_SYS_PCI_IO_SIZE,
John Rigby5f91db72008-02-26 09:38:14 -0700163 PCI_REGION_IO);
164
165 /* System memory space */
166 pci_set_region(hose->regions + 3,
167 CONFIG_PCI_SYS_MEM_BUS,
168 CONFIG_PCI_SYS_MEM_PHYS,
169 gd->ram_size,
Kumar Galaff4e66e2009-02-06 09:49:31 -0600170 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
John Rigby5f91db72008-02-26 09:38:14 -0700171
172 hose->region_count = 4;
173
174 pci_setup_indirect(hose,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 (CONFIG_SYS_IMMR + 0x8300),
176 (CONFIG_SYS_IMMR + 0x8304));
John Rigby5f91db72008-02-26 09:38:14 -0700177
178 pci_register_hose(hose);
179
180 /*
181 * Write to Command register
182 */
183 reg16 = 0xff;
184 dev = PCI_BDF(hose->first_busno, 0, 0);
185 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
186 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
187 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
188
189 /*
190 * Clear non-reserved bits in status register.
191 */
192 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
193 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
194 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
195
196#ifdef CONFIG_PCI_SCAN_SHOW
197 printf("PCI: Bus Dev VenId DevId Class Int\n");
198#endif
199 /*
200 * Hose scan.
201 */
202 hose->last_busno = pci_hose_scan(hose);
203}
204
205#if defined(CONFIG_OF_LIBFDT)
206void ft_pci_setup(void *blob, bd_t *bd)
207{
208 int nodeoffset;
209 int tmp[2];
210 const char *path;
211
212 nodeoffset = fdt_path_offset(blob, "/aliases");
213 if (nodeoffset >= 0) {
214 path = fdt_getprop(blob, nodeoffset, "pci", NULL);
215 if (path) {
216 tmp[0] = cpu_to_be32(pci_hose.first_busno);
217 tmp[1] = cpu_to_be32(pci_hose.last_busno);
218 do_fixup_by_path(blob, path, "bus-range",
219 &tmp, sizeof(tmp), 1);
220
221 tmp[0] = cpu_to_be32(gd->pci_clk);
222 do_fixup_by_path(blob, path, "clock-frequency",
223 &tmp, sizeof(tmp[0]), 1);
224 }
225 }
226}
227#endif /* CONFIG_OF_LIBFDT */