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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the R&S Protocol Board board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenke2211742002-11-02 23:30:20 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
43
wdenke2211742002-11-02 23:30:20 +000044/*
45 * select serial console configuration
46 *
47 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
49 * for SCC).
50 *
51 * if CONFIG_CONS_NONE is defined, then the serial console routines must
52 * defined elsewhere.
53 */
54#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
55#define CONFIG_CONS_ON_SCC /* define if console on SCC */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056#undef CONFIG_CONS_NONE /* define if console on neither */
wdenke2211742002-11-02 23:30:20 +000057#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
58
59/*
60 * select ethernet configuration
61 *
62 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
63 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
64 * for FCC)
65 *
66 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050067 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000068 */
69#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
70#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
71#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
72#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
73
74#if (CONFIG_ETHER_INDEX == 2)
75
76/*
77 * - Rx-CLK is CLK13
78 * - Tx-CLK is CLK14
79 * - Select bus for bd/buffers (see 28-13)
80 * - Enable Full Duplex in FSMR
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
83# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
84# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
85# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000086
87#endif /* CONFIG_ETHER_INDEX */
88
89
90/* allow to overwrite serial and ethaddr */
91#define CONFIG_ENV_OVERWRITE
92
93/* enable I2C */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020094#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
96#define CONFIG_SYS_I2C_SLAVE 0x30
wdenke2211742002-11-02 23:30:20 +000097
98
99/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
100#define CONFIG_8260_CLKIN 50000000 /* in Hz */
101
102#define CONFIG_BAUDRATE 115200
103
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500104
105/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500106 * BOOTP options
107 */
108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112
113
114/*
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#undef CONFIG_CMD_KGDB
120
wdenke2211742002-11-02 23:30:20 +0000121
122/* Define this if you want to boot from 0x00000100. If you don't define
123 * this, you will need to program the bootloader to 0xfff00000, and
124 * get the hardware reset config words at 0xfe000000. The simplest
125 * way to do that is to program the bootloader at both addresses.
126 * It is suggested that you just let U-Boot live at 0x00000000.
127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_RSD_BOOT_LOW 1
wdenke2211742002-11-02 23:30:20 +0000129
wdenke2211742002-11-02 23:30:20 +0000130#define CONFIG_BOOTDELAY 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
wdenke2211742002-11-02 23:30:20 +0000132#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
133#define CONFIG_NETMASK 255.255.0.0
134
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500135#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000136#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
137#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
138#endif
139
140/*
141 * Miscellaneous configurable options
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LONGHELP /* undef to save memory */
144#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500145#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000147#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000149#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
155#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000160
161 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000163
164/*
165 * Low Level Configuration Settings
166 * (address mappings, register initial values, etc.)
167 * You should know what you are doing if you make changes here.
168 */
169
170/*-----------------------------------------------------------------------
171 * Physical Memory Map
172 */
173#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
174#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
175
176#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
177#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
178
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200179#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
180#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
wdenke2211742002-11-02 23:30:20 +0000181
182/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
183/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
184
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200185#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
186#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
wdenke2211742002-11-02 23:30:20 +0000187
188/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
189/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
190
191#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
192#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
193
194#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
195#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
196
197#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
198
199#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
200#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_IMMR PHYS_IMMR
wdenke2211742002-11-02 23:30:20 +0000203
204/*-----------------------------------------------------------------------
205 * Reset Address
206 *
207 * In order to reset the CPU, U-Boot jumps to a special address which
208 * causes a machine check exception. The default address for this is
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
wdenke2211742002-11-02 23:30:20 +0000210 * testing the monitor in RAM using a JTAG debugger.
211 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
wdenke2211742002-11-02 23:30:20 +0000213 * cause a bus error on your hardware.
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_RESET_ADDRESS 0x20000000
wdenke2211742002-11-02 23:30:20 +0000216
217/*-----------------------------------------------------------------------
218 * Hard Reset Configuration Words
219 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if defined(CONFIG_SYS_RSD_BOOT_LOW)
222# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenke2211742002-11-02 23:30:20 +0000223#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
225#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
wdenke2211742002-11-02 23:30:20 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227/* get the HRCW ISB field from CONFIG_SYS_IMMR */
228#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
229 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
230 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenke2211742002-11-02 23:30:20 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
wdenke2211742002-11-02 23:30:20 +0000233 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234 CONFIG_SYS_RSD_HRCW_IMMR |\
wdenk8bde7f72003-06-27 21:31:46 +0000235 HRCW_MMR00 | \
236 HRCW_APPC10 | \
237 HRCW_CS10PC00 | \
238 HRCW_MODCK_H0000 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
wdenke2211742002-11-02 23:30:20 +0000240
241/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_HRCW_SLAVE1 0
243#define CONFIG_SYS_HRCW_SLAVE2 0
244#define CONFIG_SYS_HRCW_SLAVE3 0
245#define CONFIG_SYS_HRCW_SLAVE4 0
246#define CONFIG_SYS_HRCW_SLAVE5 0
247#define CONFIG_SYS_HRCW_SLAVE6 0
248#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000249
250/*-----------------------------------------------------------------------
251 * Definitions for initial stack pointer and data area (in DPRAM)
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
254#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
255#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
256#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
257#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000258
259/*-----------------------------------------------------------------------
260 * Start addresses for the final memory configuration
261 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
263 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
wdenke2211742002-11-02 23:30:20 +0000264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
266#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
267/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
269#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
270#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000271#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
273#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000274
275/*
276 * For booting Linux, the board info and command line data
277 * have to be in the first 8 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000281
282/*-----------------------------------------------------------------------
283 * FLASH and environment organization
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
286#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
289#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000290
291/* turn off NVRAM env feature */
292#undef CONFIG_NVRAM_ENV
293
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200294#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200295#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
296#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000297
298/*-----------------------------------------------------------------------
299 * Cache Configuration
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500302#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000304#endif
305
306/*-----------------------------------------------------------------------
307 * HIDx - Hardware Implementation-dependent Registers 2-11
308 *-----------------------------------------------------------------------
309 * HID0 also contains cache control - initially enable both caches and
310 * invalidate contents, then the final state leaves only the instruction
311 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
312 * but Soft reset does not.
313 *
314 * HID1 has only read-only information - nothing to set.
315 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
317#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
318#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000319
320/*-----------------------------------------------------------------------
321 * RMR - Reset Mode Register
322 *-----------------------------------------------------------------------
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_RMR 0
wdenke2211742002-11-02 23:30:20 +0000325
326/*-----------------------------------------------------------------------
327 * BCR - Bus Configuration 4-25
328 *-----------------------------------------------------------------------
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_BCR 0x100c0000
wdenke2211742002-11-02 23:30:20 +0000331
332/*-----------------------------------------------------------------------
333 * SIUMCR - SIU Module Configuration 4-31
334 *-----------------------------------------------------------------------
335 */
336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
wdenke2211742002-11-02 23:30:20 +0000338 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
339
340/*-----------------------------------------------------------------------
341 * SYPCR - System Protection Control 11-9
342 * SYPCR can only be written once after reset!
343 *-----------------------------------------------------------------------
344 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
wdenke2211742002-11-02 23:30:20 +0000347 SYPCR_SWRI | SYPCR_SWP)
348
349/*-----------------------------------------------------------------------
350 * TMCNTSC - Time Counter Status and Control 4-40
351 *-----------------------------------------------------------------------
352 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
353 * and enable Time Counter
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000356
357/*-----------------------------------------------------------------------
358 * PISCR - Periodic Interrupt Status and Control 4-42
359 *-----------------------------------------------------------------------
360 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
361 * Periodic timer
362 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000364
365/*-----------------------------------------------------------------------
366 * SCCR - System Clock Control 9-8
367 *-----------------------------------------------------------------------
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_SCCR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000370
371/*-----------------------------------------------------------------------
372 * RCCR - RISC Controller Configuration 13-7
373 *-----------------------------------------------------------------------
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000376
377/*
378 * Init Memory Controller:
379 */
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_PSDMR 0x494D2452
382#define CONFIG_SYS_LSDMR 0x49492552
wdenke2211742002-11-02 23:30:20 +0000383
384/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
386#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000387 ORxG_BCTLD | \
388 ORxG_SCY_5_CLK)
389
390/* DPRAM to the PCI BUS on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
392#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000393 ORxG_ACS_DIV4)
394
395/* 60x Bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
397#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000398 ORxS_BPD_4 | \
399 ORxS_ROWST_PBI1_A2 | \
400 ORxS_NUMR_13 | \
401 ORxS_IBID)
402
403/* Virtex-FPGA - Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
405#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
wdenk8bde7f72003-06-27 21:31:46 +0000406 ORxG_SCY_1_CLK | \
407 ORxG_ACS_DIV2 | \
408 ORxG_CSNT )
wdenke2211742002-11-02 23:30:20 +0000409
410/* local bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
412#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000413 ORxS_BPD_4 | \
414 ORxS_ROWST_PBI1_A4 | \
415 ORxS_NUMR_13)
416
417/* DPRAM to the Sharc-Bus on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
419#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000420 ORxG_ACS_DIV4)
421
422/*
423 * Internal Definitions
424 *
425 * Boot Flags
426 */
427#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
428#define BOOTFLAG_WARM 0x02 /* Software reboot */
429
430#endif /* __CONFIG_H */