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Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09001/*
2 * Copyright (C) 2007
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wolfgang Denk61fb15c52007-12-27 01:52:50 +01004 *
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09005 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/ms7722se/lowlevel_init.S
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28
29#include <asm/processor.h>
30
31/*
32 * Board specific low level init code, called _very_ early in the
33 * startup sequence. Relocation to SDRAM has not happened yet, no
34 * stack is available, bss section has not been initialised, etc.
35 *
36 * (Note: As no stack is available, no subroutines can be called...).
37 */
38
39 .global lowlevel_init
40
41 .text
42 .align 2
43
44lowlevel_init:
45
46 mov.l CCR_A, r1 ! Address of Cache Control Register
47 mov.l CCR_D, r0 ! Instruction Cache Invalidate
48 mov.l r0, @r1
49
50 mov.l MMUCR_A, r1 ! Address of MMU Control Register
51 mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
52 mov.l r0, @r1
53
54 mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010055 mov.l MSTPCR0_D, r0 !
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090056 mov.l r0, @r1
57
58 mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010059 mov.l MSTPCR2_D, r0 !
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090060 mov.l r0, @r1
61
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010062 mov.l SBSCR_A, r1 !
63 mov.w SBSCR_D, r0 !
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090064 mov.w r0, @r1
65
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010066 mov.l PSCR_A, r1 !
67 mov.w PSCR_D, r0 !
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090068 mov.w r0, @r1
69
70! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
71! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
72! mov.w r0, @r1
73
74 mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
75 mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
76 mov.w r0, @r1
77
78 mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
79 mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
80 mov.w r0, @r1
81
82 mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010083 mov.l FRQCR_D, r0 !
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090084 mov.l r0, @r1
85
86 mov.l CCR_A, r1 ! Address of Cache Control Register
87 mov.l CCR_D_2, r0 ! ??
88 mov.l r0, @r1
89
90bsc_init:
91
92 mov.l PSELA_A, r1
93 mov.w PSELA_D, r0
94 mov.w r0, @r1
95
96 mov.l DRVCR_A, r1
97 mov.w DRVCR_D, r0
98 mov.w r0, @r1
99
100 mov.l PCCR_A, r1
101 mov.w PCCR_D, r0
102 mov.w r0, @r1
103
104 mov.l PECR_A, r1
105 mov.w PECR_D, r0
106 mov.w r0, @r1
107
108 mov.l PJCR_A, r1
109 mov.w PJCR_D, r0
110 mov.w r0, @r1
111
112 mov.l PXCR_A, r1
113 mov.w PXCR_D, r0
114 mov.w r0, @r1
115
116 mov.l CMNCR_A, r1 ! CMNCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200117 mov.l CMNCR_D, r0 ! CMNCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900118 mov.l r0, @r1 ! CMNCR set
119
120 mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200121 mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900122 mov.l r0, @r1 ! CS0BCR set
123
124 mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
125 mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
126 mov.l r0, @r1 ! CS2BCR set
127
128 mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
129 mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
130 mov.l r0, @r1 ! CS4BCR set
131
132 mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200133 mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900134 mov.l r0, @r1 ! CS5ABCR set
135
136 mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200137 mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900138 mov.l r0, @r1 ! CS5BBCR set
139
140 mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200141 mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900142 mov.l r0, @r1 ! CS6ABCR set
143
144 mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200145 mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900146 mov.l r0, @r1 ! CS0WCR set
147
148 mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200149 mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900150 mov.l r0, @r1 ! CS2WCR set
151
152 mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200153 mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900154 mov.l r0, @r1 ! CS4WCR set
155
156 mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200157 mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900158 mov.l r0, @r1 ! CS5AWCR set
159
160 mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200161 mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900162 mov.l r0, @r1 ! CS5BWCR set
163
164 mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200165 mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900166 mov.l r0, @r1 ! CS6AWCR set
167
168 ! SDRAM initialization
169 mov.l SDCR_A, r1 ! SB_SDCR address -> R1
170 mov.l SDCR_D, r0 ! SB_SDCR data -> R0
171 mov.l r0, @r1 ! SB_SDCR set
172
173 mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
174 mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
175 mov.l r0, @r1 ! SB_SDWCR set
176
177 mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
178 mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
179 mov.l r0, @r1 ! SB_SDPCR set
180
181 mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
182 mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
183 mov.l r0, @r1 ! SB_RTCOR set
184
185 mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
186 mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
187 mov.l r0, @r1 ! SB_RTCSR set
188
189 mov.l SDMR3_A, r1 ! SDMR3 address -> R1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200190 mov #0x00, r0 ! SDMR3 data -> R0
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900191 mov.b r0, @r1 ! SDMR3 set
192
193 ! BL bit off (init = ON) (?!?)
194
195 stc sr, r0 ! BL bit off(init=ON)
196 mov.l SR_MASK_D, r1
197 and r1, r0
198 ldc r0, sr
199
200 rts
201 mov #0, r0
202
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900203 .align 2
204
Wolfgang Denk61fb15c52007-12-27 01:52:50 +0100205CCR_A: .long CCR
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900206MMUCR_A: .long MMUCR
207MSTPCR0_A: .long MSTPCR0
208MSTPCR2_A: .long MSTPCR2
209SBSCR_A: .long SBSCR
210PSCR_A: .long PSCR
211RWTCSR_A: .long RWTCSR
212RWTCNT_A: .long RWTCNT
213FRQCR_A: .long FRQCR
214
215CCR_D: .long 0x00000800
216CCR_D_2: .long 0x00000103
217MMUCR_D: .long 0x00000004
218MSTPCR0_D: .long 0x00001001
219MSTPCR2_D: .long 0xffffffff
220FRQCR_D: .long 0x07022538
221
222PSELA_A: .long 0xa405014E
223PSELA_D: .word 0x0A10
Wolfgang Denk61fb15c52007-12-27 01:52:50 +0100224 .align 2
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900225
226DRVCR_A: .long 0xa405018A
227DRVCR_D: .word 0x0554
228 .align 2
229
230PCCR_A: .long 0xa4050104
231PCCR_D: .word 0x8800
232 .align 2
233
234PECR_A: .long 0xa4050108
235PECR_D: .word 0x0000
236 .align 2
237
238PJCR_A: .long 0xa4050110
239PJCR_D: .word 0x1000
240 .align 2
241
242PXCR_A: .long 0xa4050148
243PXCR_D: .word 0x0AAA
244 .align 2
245
246CMNCR_A: .long CMNCR
247CMNCR_D: .long 0x00000013
248CS0BCR_A: .long CS0BCR ! Flash bank 1
249CS0BCR_D: .long 0x24920400
250CS2BCR_A: .long CS2BCR ! SRAM
251CS2BCR_D: .long 0x24920400
252CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
253CS4BCR_D: .long 0x24920400
254CS5ABCR_A: .long CS5ABCR ! Ext slot
255CS5ABCR_D: .long 0x24920400
256CS5BBCR_A: .long CS5BBCR ! USB controller
257CS5BBCR_D: .long 0x24920400
258CS6ABCR_A: .long CS6ABCR ! Ethernet
259CS6ABCR_D: .long 0x24920400
260
261CS0WCR_A: .long CS0WCR
262CS0WCR_D: .long 0x00000300
263CS2WCR_A: .long CS2WCR
264CS2WCR_D: .long 0x00000300
265CS4WCR_A: .long CS4WCR
266CS4WCR_D: .long 0x00000300
267CS5AWCR_A: .long CS5AWCR
268CS5AWCR_D: .long 0x00000300
269CS5BWCR_A: .long CS5BWCR
270CS5BWCR_D: .long 0x00000300
271CS6AWCR_A: .long CS6AWCR
272CS6AWCR_D: .long 0x00000300
273
274SDCR_A: .long SBSC_SDCR
275SDCR_D: .long 0x00020809
276SDWCR_A: .long SBSC_SDWCR
277SDWCR_D: .long 0x00164d0d
278SDPCR_A: .long SBSC_SDPCR
279SDPCR_D: .long 0x00000087
280RTCOR_A: .long SBSC_RTCOR
281RTCOR_D: .long 0xA55A0034
282RTCSR_A: .long SBSC_RTCSR
283RTCSR_D: .long 0xA55A0010
284SDMR3_A: .long 0xFE500180
285
286 .align 1
287
288SBSCR_D: .word 0x0040
289PSCR_D: .word 0x0000
290RWTCSR_D_1: .word 0xA507
291RWTCSR_D_2: .word 0xA507
292RWTCNT_D: .word 0x5A00
293
294SR_MASK_D: .long 0xEFFFFF0F