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Marek Vasut10da95a2010-07-26 06:30:25 +02001/*
2 * Balloon3 configuration file
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * High Level Board Configuration Options
27 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010028#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
Marek Vasut10da95a2010-07-26 06:30:25 +020029#define CONFIG_BALLOON3 1 /* Balloon3 board */
30
31/*
32 * Environment settings
33 */
34#define CONFIG_ENV_OVERWRITE
35#define CONFIG_SYS_MALLOC_LEN (128*1024)
Marek Vasut20ae5192010-10-03 01:05:55 +020036#define CONFIG_ARCH_CPU_INIT
Marek Vasut10da95a2010-07-26 06:30:25 +020037#define CONFIG_BOOTCOMMAND \
Marek Vasut20ae5192010-10-03 01:05:55 +020038 "fpga load 0x0 0x50000 0x62638; " \
Marek Vasut10da95a2010-07-26 06:30:25 +020039 "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
40 "bootm 0xa4000000; " \
41 "fi; " \
Marek Vasut20ae5192010-10-03 01:05:55 +020042 "bootm 0xd0000;"
Marek Vasut10da95a2010-07-26 06:30:25 +020043#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
44#define CONFIG_TIMESTAMP
45#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
46#define CONFIG_CMDLINE_TAG
47#define CONFIG_SETUP_MEMORY_TAGS
Marek Vasut20ae5192010-10-03 01:05:55 +020048#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasut10da95a2010-07-26 06:30:25 +020049#define CONFIG_LZMA /* LZMA compression support */
50
51/*
52 * Serial Console Configuration
53 */
54#define CONFIG_PXA_SERIAL
55#define CONFIG_STUART 1
56#define CONFIG_BAUDRATE 115200
57#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
58
59/*
60 * Bootloader Components Configuration
61 */
62#include <config_cmd_default.h>
63
64#undef CONFIG_CMD_NET
Sebastien Carlier6d8962e2010-11-05 15:48:07 +010065#undef CONFIG_CMD_NFS
Marek Vasut10da95a2010-07-26 06:30:25 +020066#undef CONFIG_CMD_ENV
67#undef CONFIG_CMD_IMLS
68#define CONFIG_CMD_USB
69#define CONFIG_CMD_FPGA
70#undef CONFIG_LCD
71
72/*
73 * KGDB
74 */
75#ifdef CONFIG_CMD_KGDB
76#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
77#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
78#endif
79
80/*
81 * HUSH Shell Configuration
82 */
83#define CONFIG_SYS_HUSH_PARSER 1
84#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
85
86#define CONFIG_SYS_LONGHELP
87#ifdef CONFIG_SYS_HUSH_PARSER
88#define CONFIG_SYS_PROMPT "$ "
89#else
90#define CONFIG_SYS_PROMPT "=> "
91#endif
92#define CONFIG_SYS_CBSIZE 256
93#define CONFIG_SYS_PBSIZE \
94 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
95#define CONFIG_SYS_MAXARGS 16
96#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
97#define CONFIG_SYS_DEVICE_NULLDEV 1
98
99/*
100 * Clock Configuration
101 */
102#undef CONFIG_SYS_CLKS_IN_HZ
103#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
104#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
105
106/*
107 * Stack sizes
108 */
109#define CONFIG_STACKSIZE (128*1024) /* regular stack */
110#ifdef CONFIG_USE_IRQ
111#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
112#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
113#endif
114
115/*
116 * DRAM Map
117 */
118#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
119#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
120#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
121#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
122#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
123#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
124#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
125
126#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
127#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
128
129#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
130#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
131
132#define CONFIG_SYS_LOAD_ADDR 0xa1000000
133
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200134#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut20ae5192010-10-03 01:05:55 +0200135#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200136 (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200137
Marek Vasut10da95a2010-07-26 06:30:25 +0200138/*
139 * NOR FLASH
140 */
141#ifdef CONFIG_CMD_FLASH
142#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
143#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
144#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
145
146#define CONFIG_SYS_FLASH_CFI
147#define CONFIG_FLASH_CFI_DRIVER 1
148#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
149
150#define CONFIG_SYS_MAX_FLASH_BANKS 1
151#define CONFIG_SYS_MAX_FLASH_SECT 256
152
153#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
154
155#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
156#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
157#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
158#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
159#define CONFIG_SYS_FLASH_PROTECTION
160#define CONFIG_ENV_IS_IN_FLASH
161#else
162#define CONFIG_SYS_NO_FLASH
163#define CONFIG_SYS_ENV_IS_NOWHERE
164#endif
165
166#define CONFIG_SYS_MONITOR_BASE 0x000000
167#define CONFIG_SYS_MONITOR_LEN 0x40000
168
169#define CONFIG_ENV_SIZE 0x2000
170#define CONFIG_ENV_ADDR 0x40000
171#define CONFIG_ENV_SECT_SIZE 0x10000
172
173/*
174 * GPIO settings
175 */
176#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
177#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
178#define CONFIG_SYS_GPSR2_VAL 0x7131c000
179#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
180
181#define CONFIG_SYS_GPCR0_VAL 0x0
182#define CONFIG_SYS_GPCR1_VAL 0x0
183#define CONFIG_SYS_GPCR2_VAL 0x0
184#define CONFIG_SYS_GPCR3_VAL 0x0
185
186#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
187#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
188#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
189#define CONFIG_SYS_GPDR3_VAL 0x000201fe
190
191#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
192#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
193#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
194#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
195#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
196#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
197#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
198#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
199
200#define CONFIG_SYS_PSSR_VAL 0x30
201
202/*
203 * Clock settings
204 */
205#define CONFIG_SYS_CKEN 0xffffffff
206#define CONFIG_SYS_CCCR 0x00000290
207
208/*
209 * Memory settings
210 */
211#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
212#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
213#define CONFIG_SYS_MSC2_VAL 0x74a42491
214#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
215#define CONFIG_SYS_MDREFR_VAL 0x001d8018
216#define CONFIG_SYS_MDMRS_VAL 0x00220022
217#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
218#define CONFIG_SYS_SXCNFG_VAL 0x00000000
219#define CONFIG_SYS_MEM_BUF_IMP 0x0f
220
221/*
222 * PCMCIA and CF Interfaces
223 */
224#define CONFIG_SYS_MECR_VAL 0x00000000
225#define CONFIG_SYS_MCMEM0_VAL 0x00014307
226#define CONFIG_SYS_MCMEM1_VAL 0x00014307
227#define CONFIG_SYS_MCATT0_VAL 0x0001c787
228#define CONFIG_SYS_MCATT1_VAL 0x0001c787
229#define CONFIG_SYS_MCIO0_VAL 0x0001430f
230#define CONFIG_SYS_MCIO1_VAL 0x0001430f
231
232/*
233 * LCD
234 */
235#ifdef CONFIG_LCD
236#define CONFIG_BALLOON3LCD
237#define CONFIG_VIDEO_LOGO
238#define CONFIG_CMD_BMP
239#define CONFIG_SPLASH_SCREEN
240#define CONFIG_SPLASH_SCREEN_ALIGN
241#define CONFIG_VIDEO_BMP_GZIP
242#define CONFIG_VIDEO_BMP_RLE8
243#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
244#endif
245
246/*
247 * USB
248 */
249#ifdef CONFIG_CMD_USB
250#define CONFIG_USB_OHCI_NEW
251#define CONFIG_SYS_USB_OHCI_CPU_INIT
252#define CONFIG_SYS_USB_OHCI_BOARD_INIT
253#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
254#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
255#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
256#define CONFIG_USB_STORAGE
257#define CONFIG_DOS_PARTITION
258#define CONFIG_CMD_FAT
259#define CONFIG_CMD_EXT2
260#endif
261
262/*
263 * FPGA
264 */
265#ifdef CONFIG_CMD_FPGA
266#define CONFIG_FPGA
267#define CONFIG_FPGA_XILINX
268#define CONFIG_FPGA_SPARTAN3
269#define CONFIG_SYS_FPGA_PROG_FEEDBACK
270#define CONFIG_SYS_FPGA_WAIT 1000
271#define CONFIG_MAX_FPGA_DEVICES 1
272#endif
273
274#endif /* __CONFIG_H */