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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8b0592b89e0f9f81c9e150c81d96f8a43e4d6101 / . / include / configs / XPEDITE5370.h
blob: 3bc0fe8f67639be9551508e52182946de6556d23 [file] [log] [blame]
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]1/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * xpedite5370 board configuration file
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8572 1
37#define CONFIG_XPEDITE5370 1
38#define CONFIG_SYS_BOARD_NAME "XPedite5370"
39#define CONFIG_NUM_CPUS 2 /* 2 Cores */
40#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
41#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
42
43#define CONFIG_PCI 1 /* Enable PCI/PCIE */
44#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
45#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
46#define CONFIG_PCIE1 1 /* PCIE controler 1 */
47#define CONFIG_PCIE2 1 /* PCIE controler 2 */
48#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
49#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
50#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
51#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52
53/*
54 * DDR config
55 */
56#define CONFIG_FSL_DDR2
57#undef CONFIG_FSL_DDR_INTERACTIVE
58#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
59#define CONFIG_DDR_SPD
60#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
61#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
62#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
63#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
64#define CONFIG_NUM_DDR_CONTROLLERS 2
65#define CONFIG_DIMM_SLOTS_PER_CTLR 1
66#define CONFIG_CHIP_SELECTS_PER_CTRL 1
67#define CONFIG_DDR_ECC
68#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
69#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
70#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71#define CONFIG_VERY_BIG_RAM
72
73#ifndef __ASSEMBLY__
74extern unsigned long get_board_sys_clk(unsigned long dummy);
75extern unsigned long get_board_ddr_clk(unsigned long dummy);
76#endif
77
78#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
79#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
80
81/*
82 * These can be toggled for performance analysis, otherwise use default.
83 */
84#define CONFIG_L2_CACHE /* toggle L2 cache */
85#define CONFIG_BTB /* toggle branch predition */
86#define CONFIG_ENABLE_36BIT_PHYS 1
87
88/*
89 * Base addresses -- Note these are effective addresses where the
90 * actual resources get mapped (not physical addresses)
91 */
92#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
93#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
94#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
95#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
96#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
97#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
98
99/*
100 * Diagnostics
101 */
102#define CONFIG_SYS_ALT_MEMTEST
103#define CONFIG_SYS_MEMTEST_START 0x10000000
104#define CONFIG_SYS_MEMTEST_END 0x20000000
105
106/*
107 * Memory map
108 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
109 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
110 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
111 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
112 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
113 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
114 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
115 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
116 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
117 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
118 */
119
120#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
121
122/*
123 * NAND flash configuration
124 */
125#define CONFIG_SYS_NAND_BASE 0xef800000
126#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
127
128/*
129 * NOR flash configuration
130 */
131#define CONFIG_SYS_FLASH_BASE 0xf8000000
132#define CONFIG_SYS_FLASH_BASE2 0xf0000000
133#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
134#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
135#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
136#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
138#define CONFIG_FLASH_CFI_DRIVER
139#define CONFIG_SYS_FLASH_CFI
140#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
141 {0xf7f40000, 0xc0000} }
142#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
143
144/*
145 * Chip select configuration
146 */
147/* NOR Flash 0 on CS0 */
148#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
149 BR_PS_16 | \
150 BR_V)
151#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
152 OR_GPCM_CSNT | \
153 OR_GPCM_XACS | \
154 OR_GPCM_ACS_DIV2 | \
155 OR_GPCM_SCY_8 | \
156 OR_GPCM_TRLX | \
157 OR_GPCM_EHTR | \
158 OR_GPCM_EAD)
159
160/* NOR Flash 1 on CS1 */
161#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
162 BR_PS_16 | \
163 BR_V)
164#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
165
166/* NAND flash on CS2 */
167#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
168 (2<<BR_DECC_SHIFT) | \
169 BR_PS_8 | \
170 BR_MS_FCM | \
171 BR_V)
172
173/* NAND flash on CS2 */
174#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
175 OR_FCM_PGS | \
176 OR_FCM_CSCT | \
177 OR_FCM_CST | \
178 OR_FCM_CHT | \
179 OR_FCM_SCY_1 | \
180 OR_FCM_TRLX | \
181 OR_FCM_EHTR)
182
183/* NAND flash on CS3 */
184#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
185 (2<<BR_DECC_SHIFT) | \
186 BR_PS_8 | \
187 BR_MS_FCM | \
188 BR_V)
189#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
190
191/*
192 * Use L1 as initial stack
193 */
194#define CONFIG_SYS_INIT_RAM_LOCK 1
195#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
196#define CONFIG_SYS_INIT_RAM_END 0x00004000
197
198#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
203#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
204
205/*
206 * Serial Port
207 */
208#define CONFIG_CONS_INDEX 1
209#define CONFIG_SYS_NS16550
210#define CONFIG_SYS_NS16550_SERIAL
211#define CONFIG_SYS_NS16550_REG_SIZE 1
212#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
213#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
214#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
215#define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217#define CONFIG_BAUDRATE 115200
218#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
219#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
220
221/*
222 * Use the HUSH parser
223 */
224#define CONFIG_SYS_HUSH_PARSER
225#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
226
227/*
228 * Pass open firmware flat tree
229 */
230#define CONFIG_OF_LIBFDT 1
231#define CONFIG_OF_BOARD_SETUP 1
232#define CONFIG_OF_STDOUT_VIA_ALIAS 1
233
234#define CONFIG_SYS_64BIT_VSPRINTF 1
235#define CONFIG_SYS_64BIT_STRTOUL 1
236
237/*
238 * I2C
239 */
240#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
241#define CONFIG_HARD_I2C /* I2C with hardware support */
242#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
243#define CONFIG_SYS_I2C_SLAVE 0x7F
244#define CONFIG_SYS_I2C_OFFSET 0x3000
245#define CONFIG_SYS_I2C2_OFFSET 0x3100
246#define CONFIG_I2C_MULTI_BUS
247#define CONFIG_I2C_CMD_TREE
248
249/* PEX8518 slave I2C interface */
250#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
251
252/* I2C DS1631 temperature sensor */
253#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
254#define CONFIG_DTT_DS1621
255#define CONFIG_DTT_SENSORS { 0 }
256
257/* I2C EEPROM - AT24C128B */
258#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
259#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
260#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
261#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
262
263/* I2C RTC */
264#define CONFIG_RTC_M41T11 1
265#define CONFIG_SYS_I2C_RTC_ADDR 0x68
266#define CONFIG_SYS_M41T11_BASE_YEAR 2000
267
268/* GPIO/EEPROM/SRAM */
269#define CONFIG_DS4510
270#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
271
272/* GPIO */
273#define CONFIG_PCA953X
274#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
275#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
276#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
277#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
278#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
279
280/*
281 * PU = pulled high, PD = pulled low
282 * I = input, O = output, IO = input/output
283 */
284/* PCA9557 @ 0x18*/
285#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
286#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
287#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
288#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
289#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
290#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
291#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
292#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
293
294/* PCA9557 @ 0x1c*/
295#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
296#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
297#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
298#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
299#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
300#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
301#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
302#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
303
304/* PCA9557 @ 0x1e*/
305#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
306#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
307#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
308#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
309#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
310#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
311#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
312
313/* PCA9557 @ 0x1f */
314#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
315#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
316#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
317#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
318#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
319
320/*
321 * General PCI
322 * Memory space is mapped 1-1, but I/O space must start from 0.
323 */
324/* PCIE1 - VPX P1 */
325#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
326#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
327#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
328#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
329#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
330#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
331
332/* PCIE2 - PEX8518 */
333#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
334#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
335#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
336#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
337#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
338#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
339
340/*
341 * Networking options
342 */
343#define CONFIG_TSEC_ENET /* tsec ethernet support */
344#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
345#define CONFIG_NET_MULTI 1
346#define CONFIG_TSEC_TBI
347#define CONFIG_MII 1 /* MII PHY management */
348#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
349#define CONFIG_ETHPRIME "eTSEC2"
350
351#define CONFIG_TSEC1 1
352#define CONFIG_TSEC1_NAME "eTSEC1"
353#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
354#define TSEC1_PHY_ADDR 1
355#define TSEC1_PHYIDX 0
356#define CONFIG_HAS_ETH0
357
358#define CONFIG_TSEC2 1
359#define CONFIG_TSEC2_NAME "eTSEC2"
360#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
361#define TSEC2_PHY_ADDR 2
362#define TSEC2_PHYIDX 0
363#define CONFIG_HAS_ETH1
364
365/*
366 * Command configuration.
367 */
368#include <config_cmd_default.h>
369
370#define CONFIG_CMD_ASKENV
371#define CONFIG_CMD_DATE
372#define CONFIG_CMD_DHCP
373#define CONFIG_CMD_DS4510
374#define CONFIG_CMD_DS4510_INFO
375#define CONFIG_CMD_DTT
376#define CONFIG_CMD_EEPROM
377#define CONFIG_CMD_ELF
378#define CONFIG_CMD_ENV
379#define CONFIG_CMD_FLASH
380#define CONFIG_CMD_I2C
381#define CONFIG_CMD_JFFS2
382#define CONFIG_CMD_MII
383#define CONFIG_CMD_NET
384#define CONFIG_CMD_PCA953X
385#define CONFIG_CMD_PCA953X_INFO
386#define CONFIG_CMD_PCI
387#define CONFIG_CMD_PING
388#define CONFIG_CMD_SNTP
389
390/*
391 * Miscellaneous configurable options
392 */
393#define CONFIG_SYS_LONGHELP /* undef to save memory */
394#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
395#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
396#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
397#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
398#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
399#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
400#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
401#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
402#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
403#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
404#define CONFIG_PANIC_HANG /* do not reset board on panic */
405#define CONFIG_PREBOOT /* enable preboot variable */
406#define CONFIG_FIT 1
407#define CONFIG_FIT_VERBOSE 1
408#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
409
410/*
411 * For booting Linux, the board info and command line data
412 * have to be in the first 16 MB of memory, since this is
413 * the maximum mapped by the Linux kernel during initialization.
414 */
415#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
416
417/*
418 * Boot Flags
419 */
420#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
421#define BOOTFLAG_WARM 0x02 /* Software reboot */
422
423/*
424 * Environment Configuration
425 */
426#define CONFIG_ENV_IS_IN_FLASH 1
427#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
428#define CONFIG_ENV_SIZE 0x8000
429#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
430
431/*
432 * Flash memory map:
433 * fff80000 - ffffffff Pri U-Boot (512 KB)
434 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
435 * fff00000 - fff3ffff Pri FDT (256KB)
436 * fef00000 - ffefffff Pri OS image (16MB)
437 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
438 *
439 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
440 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
441 * f7f00000 - f7f3ffff Sec FDT (256KB)
442 * f6f00000 - f7efffff Sec OS image (16MB)
443 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
444 */
445#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
446#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
447#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
448#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
449#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
450#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
451
452#define CONFIG_PROG_UBOOT1 \
453 "$download_cmd $loadaddr $ubootfile; " \
454 "if test $? -eq 0; then " \
455 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
456 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
457 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
458 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
459 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
460 "if test $? -ne 0; then " \
461 "echo PROGRAM FAILED; " \
462 "else; " \
463 "echo PROGRAM SUCCEEDED; " \
464 "fi; " \
465 "else; " \
466 "echo DOWNLOAD FAILED; " \
467 "fi;"
468
469#define CONFIG_PROG_UBOOT2 \
470 "$download_cmd $loadaddr $ubootfile; " \
471 "if test $? -eq 0; then " \
472 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
473 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
474 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
475 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
476 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
477 "if test $? -ne 0; then " \
478 "echo PROGRAM FAILED; " \
479 "else; " \
480 "echo PROGRAM SUCCEEDED; " \
481 "fi; " \
482 "else; " \
483 "echo DOWNLOAD FAILED; " \
484 "fi;"
485
486#define CONFIG_BOOT_OS_NET \
487 "$download_cmd $osaddr $osfile; " \
488 "if test $? -eq 0; then " \
489 "if test -n $fdtaddr; then " \
490 "$download_cmd $fdtaddr $fdtfile; " \
491 "if test $? -eq 0; then " \
492 "bootm $osaddr - $fdtaddr; " \
493 "else; " \
494 "echo FDT DOWNLOAD FAILED; " \
495 "fi; " \
496 "else; " \
497 "bootm $osaddr; " \
498 "fi; " \
499 "else; " \
500 "echo OS DOWNLOAD FAILED; " \
501 "fi;"
502
503#define CONFIG_PROG_OS1 \
504 "$download_cmd $osaddr $osfile; " \
505 "if test $? -eq 0; then " \
506 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
507 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
508 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
509 "if test $? -ne 0; then " \
510 "echo OS PROGRAM FAILED; " \
511 "else; " \
512 "echo OS PROGRAM SUCCEEDED; " \
513 "fi; " \
514 "else; " \
515 "echo OS DOWNLOAD FAILED; " \
516 "fi;"
517
518#define CONFIG_PROG_OS2 \
519 "$download_cmd $osaddr $osfile; " \
520 "if test $? -eq 0; then " \
521 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
522 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
523 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
524 "if test $? -ne 0; then " \
525 "echo OS PROGRAM FAILED; " \
526 "else; " \
527 "echo OS PROGRAM SUCCEEDED; " \
528 "fi; " \
529 "else; " \
530 "echo OS DOWNLOAD FAILED; " \
531 "fi;"
532
533#define CONFIG_PROG_FDT1 \
534 "$download_cmd $fdtaddr $fdtfile; " \
535 "if test $? -eq 0; then " \
536 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
537 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
538 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
539 "if test $? -ne 0; then " \
540 "echo FDT PROGRAM FAILED; " \
541 "else; " \
542 "echo FDT PROGRAM SUCCEEDED; " \
543 "fi; " \
544 "else; " \
545 "echo FDT DOWNLOAD FAILED; " \
546 "fi;"
547
548#define CONFIG_PROG_FDT2 \
549 "$download_cmd $fdtaddr $fdtfile; " \
550 "if test $? -eq 0; then " \
551 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
552 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
553 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
554 "if test $? -ne 0; then " \
555 "echo FDT PROGRAM FAILED; " \
556 "else; " \
557 "echo FDT PROGRAM SUCCEEDED; " \
558 "fi; " \
559 "else; " \
560 "echo FDT DOWNLOAD FAILED; " \
561 "fi;"
562
563#define CONFIG_EXTRA_ENV_SETTINGS \
564 "autoload=yes\0" \
565 "download_cmd=tftp\0" \
566 "console_args=console=ttyS0,115200\0" \
567 "root_args=root=/dev/nfs rw\0" \
568 "misc_args=ip=on\0" \
569 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
570 "bootfile=/home/user/file\0" \
571 "osfile=/home/user/uImage-XPedite5370\0" \
572 "fdtfile=/home/user/xpedite5370.dtb\0" \
573 "ubootfile=/home/user/u-boot.bin\0" \
574 "fdtaddr=c00000\0" \
575 "osaddr=0x1000000\0" \
576 "loadaddr=0x1000000\0" \
577 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
578 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
579 "prog_os1="CONFIG_PROG_OS1"\0" \
580 "prog_os2="CONFIG_PROG_OS2"\0" \
581 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
582 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
583 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
584 "bootcmd_flash1=run set_bootargs; " \
585 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
586 "bootcmd_flash2=run set_bootargs; " \
587 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
588 "bootcmd=run bootcmd_flash1\0"
589#endif /* __CONFIG_H */