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wdenk0db5bca2003-03-31 17:27:09 +00001/*
2 * (C) Copyright 2003
3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
wdenk8bde7f72003-06-27 21:31:46 +000020 * Foundation,
wdenk0db5bca2003-03-31 17:27:09 +000021 */
22
23/*
24 * File: cmi_mpc5xx.h
wdenk8bde7f72003-06-27 21:31:46 +000025 *
26 * Discription: Config header file for cmi
wdenk0db5bca2003-03-31 17:27:09 +000027 * board using an MPC5xx CPU
28 *
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 */
37
38#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
39#define CONFIG_CMI 1 /* Using the customized cmi board */
40
41/* Serial Console Configuration */
42#define CONFIG_5xx_CONS_SCI1
43#undef CONFIG_5xx_CONS_SCI2
44
45#define CONFIG_BAUDRATE 57600
46
47#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
48 CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \
49 CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \
50 CFG_CMD_IMI)
51
52/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
53#include <cmd_confdefs.h>
54
55#if 0
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
61
62#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
63
64#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
65
wdenk8bde7f72003-06-27 21:31:46 +000066#define CONFIG_STATUS_LED 1 /* Enable status led */
wdenk0db5bca2003-03-31 17:27:09 +000067
68#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
69
70/*
wdenk8bde7f72003-06-27 21:31:46 +000071 * Miscellaneous configurable options
wdenk0db5bca2003-03-31 17:27:09 +000072 */
73
74#define CFG_LONGHELP /* undef to save memory */
75#define CFG_PROMPT "=> " /* Monitor Command Prompt */
76#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
77#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
78#else
79#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
80#endif
81#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
82#define CFG_MAXARGS 16 /* max number of command args */
83#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
84
85#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
86#define CFG_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
87
88#define CFG_LOAD_ADDR 0x100000 /* default load address */
89
90#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
91
92#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
93
94
95/*
96 * Low Level Configuration Settings
97 */
98
99/*
100 * Internal Memory Mapped (This is not the IMMR content)
101 */
102#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */
103
104/*
105 * Definitions for initial stack pointer and data area
106 */
wdenk8bde7f72003-06-27 21:31:46 +0000107#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
wdenk0db5bca2003-03-31 17:27:09 +0000108#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
109#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
110#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
111#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
112
113/*
114 * Start addresses for the final memory configuration
115 * Please note that CFG_SDRAM_BASE _must_ start at 0
116 */
117#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
118#define CFG_FLASH_BASE 0x02000000 /* External flash */
119#define PLD_BASE 0x03000000 /* PLD */
120#define ANYBUS_BASE 0x03010000 /* Anybus Module */
121
122#define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */
123#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
124 /* This adress is given to the linker with -Ttext to */
125 /* locate the text section at this adress. */
126#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
127#define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
128
129/*
130 * For booting Linux, the board info and command line data
131 * have to be in the first 8 MB of memory, since this is
132 * the maximum mapped by the Linux kernel during initialization.
133 */
134#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
135
136
137/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000138 * FLASH organization
wdenk0db5bca2003-03-31 17:27:09 +0000139 *-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000140 *
wdenk0db5bca2003-03-31 17:27:09 +0000141 */
142
143#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
144#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
145#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
146#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
147#define CFG_FLASH_PROTECTION 1 /* Physically section protection on */
148
149#define CFG_ENV_IS_IN_FLASH 1
150
151#ifdef CFG_ENV_IS_IN_FLASH
152#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
153#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
154#endif
155
156/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000157 * SYPCR - System Protection Control
wdenk0db5bca2003-03-31 17:27:09 +0000158 * SYPCR can only be written once after reset!
159 *-----------------------------------------------------------------------
160 * SW Watchdog freeze
161 */
162#if defined(CONFIG_WATCHDOG)
163#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
164 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
165#else
166#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000167 SYPCR_SWP)
wdenk0db5bca2003-03-31 17:27:09 +0000168#endif /* CONFIG_WATCHDOG */
169
170/*-----------------------------------------------------------------------
171 * TBSCR - Time Base Status and Control
172 *-----------------------------------------------------------------------
173 * Clear Reference Interrupt Status, Timebase freezing enabled
174 */
175#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
176
177/*-----------------------------------------------------------------------
178 * PISCR - Periodic Interrupt Status and Control
179 *-----------------------------------------------------------------------
180 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
181 */
182#define CFG_PISCR (PISCR_PITF)
183
184/*-----------------------------------------------------------------------
185 * SCCR - System Clock and reset Control Register
186 *-----------------------------------------------------------------------
187 * Set clock output, timebase and RTC source and divider,
188 * power management and some other internal clocks
189 */
190#define SCCR_MASK SCCR_EBDF00
191#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
192 SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
193
194/*-----------------------------------------------------------------------
195 * SIUMCR - SIU Module Configuration
196 *-----------------------------------------------------------------------
197 * Data show cycle
198 */
199#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
200
201/*-----------------------------------------------------------------------
202 * PLPRCR - PLL, Low-Power, and Reset Control Register
203 *-----------------------------------------------------------------------
204 * Set all bits to 40 Mhz
wdenk8bde7f72003-06-27 21:31:46 +0000205 *
wdenk0db5bca2003-03-31 17:27:09 +0000206 */
207#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
208#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
wdenk8bde7f72003-06-27 21:31:46 +0000209
wdenk0db5bca2003-03-31 17:27:09 +0000210
211/*-----------------------------------------------------------------------
212 * UMCR - UIMB Module Configuration Register
213 *-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000214 *
wdenk0db5bca2003-03-31 17:27:09 +0000215 */
216#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
217
218/*-----------------------------------------------------------------------
219 * ICTRL - I-Bus Support Control Register
220 */
wdenk8bde7f72003-06-27 21:31:46 +0000221#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
wdenk0db5bca2003-03-31 17:27:09 +0000222
223/*-----------------------------------------------------------------------
224 * USIU - Memory Controller Register
wdenk8bde7f72003-06-27 21:31:46 +0000225 *-----------------------------------------------------------------------
wdenk0db5bca2003-03-31 17:27:09 +0000226 */
227
wdenk8bde7f72003-06-27 21:31:46 +0000228#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
wdenk0db5bca2003-03-31 17:27:09 +0000229#define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
230#define CFG_BR1_PRELIM (ANYBUS_BASE)
231#define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
232#define CFG_BR2_PRELIM (CFG_SDRAM_BASE | BR_V | BR_PS_32)
233#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
234#define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
235#define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
236 OR_ACS_10 | OR_ETHR | OR_CSNT)
237
238#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
239
240/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000241 * DER - Timer Decrementer
wdenk0db5bca2003-03-31 17:27:09 +0000242 *-----------------------------------------------------------------------
243 * Initialise to zero
244 */
245#define CFG_DER 0x00000000
246
247
248/*
249 * Internal Definitions
250 *
251 * Boot Flags
252 */
253#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
254#define BOOTFLAG_WARM 0x02 /* Software reboot */
255
256#endif /* __CONFIG_H */