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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutf5f69592017-09-15 21:13:56 +02002/*
3 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
Marek Vasutf5f69592017-09-15 21:13:56 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -07009#include <malloc.h>
Simon Glass401d1c42020-10-30 21:38:53 -060010#include <asm/global_data.h>
Simon Glass336d4612020-02-03 07:36:16 -070011#include <dm/device_compat.h>
Marek Vasutfbf26be2019-04-21 22:46:25 +020012#include <dm/pinctrl.h>
Marek Vasutf5f69592017-09-15 21:13:56 +020013#include <errno.h>
14#include <asm/gpio.h>
15#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Marek Vasut52c80342017-11-26 18:08:53 +010017#include "../pinctrl/renesas/sh_pfc.h"
Marek Vasutf5f69592017-09-15 21:13:56 +020018
19#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
20#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
21#define GPIO_OUTDT 0x08 /* General Output Register */
22#define GPIO_INDT 0x0c /* General Input Register */
23#define GPIO_INTDT 0x10 /* Interrupt Display Register */
24#define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
25#define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
26#define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
27#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
28#define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
29#define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
30#define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
Marek Vasute9c9e9c2021-04-27 21:29:50 +020031#define GPIO_INEN 0x50 /* General Input Enable Register */
Marek Vasutf5f69592017-09-15 21:13:56 +020032
33#define RCAR_MAX_GPIO_PER_BANK 32
34
Marek Vasute9c9e9c2021-04-27 21:29:50 +020035#define RCAR_GPIO_HAS_INEN BIT(0)
36
Marek Vasutf5f69592017-09-15 21:13:56 +020037DECLARE_GLOBAL_DATA_PTR;
38
39struct rcar_gpio_priv {
Marek Vasut52c80342017-11-26 18:08:53 +010040 void __iomem *regs;
Marek Vasute9c9e9c2021-04-27 21:29:50 +020041 u32 quirks;
Marek Vasut52c80342017-11-26 18:08:53 +010042 int pfc_offset;
Marek Vasutf5f69592017-09-15 21:13:56 +020043};
44
45static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
46{
47 struct rcar_gpio_priv *priv = dev_get_priv(dev);
48 const u32 bit = BIT(offset);
49
50 /*
51 * Testing on r8a7790 shows that INDT does not show correct pin state
52 * when configured as output, so use OUTDT in case of output pins.
53 */
54 if (readl(priv->regs + GPIO_INOUTSEL) & bit)
55 return !!(readl(priv->regs + GPIO_OUTDT) & bit);
56 else
57 return !!(readl(priv->regs + GPIO_INDT) & bit);
58}
59
60static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
61 int value)
62{
63 struct rcar_gpio_priv *priv = dev_get_priv(dev);
64
65 if (value)
66 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
67 else
68 clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
69
70 return 0;
71}
72
Marek Vasutf10de232021-04-27 21:17:43 +020073static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
Marek Vasutf5f69592017-09-15 21:13:56 +020074 bool output)
75{
Marek Vasutf10de232021-04-27 21:17:43 +020076 struct rcar_gpio_priv *priv = dev_get_priv(dev);
77 void __iomem *regs = priv->regs;
78
Marek Vasutf5f69592017-09-15 21:13:56 +020079 /*
80 * follow steps in the GPIO documentation for
81 * "Setting General Output Mode" and
82 * "Setting General Input Mode"
83 */
84
85 /* Configure postive logic in POSNEG */
86 clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
87
Marek Vasute9c9e9c2021-04-27 21:29:50 +020088 /* Select "Input Enable/Disable" in INEN */
89 if (priv->quirks & RCAR_GPIO_HAS_INEN) {
90 if (output)
91 clrbits_le32(regs + GPIO_INEN, BIT(offset));
92 else
93 setbits_le32(regs + GPIO_INEN, BIT(offset));
94 }
95
Marek Vasutf5f69592017-09-15 21:13:56 +020096 /* Select "General Input/Output Mode" in IOINTSEL */
97 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
98
99 /* Select Input Mode or Output Mode in INOUTSEL */
100 if (output)
101 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
102 else
103 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
104}
105
106static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
107{
Marek Vasutf10de232021-04-27 21:17:43 +0200108 rcar_gpio_set_direction(dev, offset, false);
Marek Vasutf5f69592017-09-15 21:13:56 +0200109
110 return 0;
111}
112
113static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
114 int value)
115{
Marek Vasutf5f69592017-09-15 21:13:56 +0200116 /* write GPIO value to output before selecting output mode of pin */
117 rcar_gpio_set_value(dev, offset, value);
Marek Vasutf10de232021-04-27 21:17:43 +0200118 rcar_gpio_set_direction(dev, offset, true);
Marek Vasutf5f69592017-09-15 21:13:56 +0200119
120 return 0;
121}
122
123static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
124{
125 struct rcar_gpio_priv *priv = dev_get_priv(dev);
126
127 if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
128 return GPIOF_OUTPUT;
129 else
130 return GPIOF_INPUT;
131}
132
133static const struct dm_gpio_ops rcar_gpio_ops = {
Pali Rohára74931a2022-08-02 12:06:55 +0200134 .request = pinctrl_gpio_request,
135 .rfree = pinctrl_gpio_free,
Marek Vasutf5f69592017-09-15 21:13:56 +0200136 .direction_input = rcar_gpio_direction_input,
137 .direction_output = rcar_gpio_direction_output,
138 .get_value = rcar_gpio_get_value,
139 .set_value = rcar_gpio_set_value,
140 .get_function = rcar_gpio_get_function,
141};
142
143static int rcar_gpio_probe(struct udevice *dev)
144{
145 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
146 struct rcar_gpio_priv *priv = dev_get_priv(dev);
147 struct fdtdec_phandle_args args;
148 struct clk clk;
149 int node = dev_of_offset(dev);
150 int ret;
151
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900152 priv->regs = dev_read_addr_ptr(dev);
Marek Vasute9c9e9c2021-04-27 21:29:50 +0200153 priv->quirks = dev_get_driver_data(dev);
Marek Vasutf5f69592017-09-15 21:13:56 +0200154 uc_priv->bank_name = dev->name;
155
156 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
157 NULL, 3, 0, &args);
Marek Vasut52c80342017-11-26 18:08:53 +0100158 priv->pfc_offset = ret == 0 ? args.args[1] : -1;
Marek Vasutf5f69592017-09-15 21:13:56 +0200159 uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
160
161 ret = clk_get_by_index(dev, 0, &clk);
162 if (ret < 0) {
163 dev_err(dev, "Failed to get GPIO bank clock\n");
164 return ret;
165 }
166
167 ret = clk_enable(&clk);
168 clk_free(&clk);
169 if (ret) {
170 dev_err(dev, "Failed to enable GPIO bank clock\n");
171 return ret;
172 }
173
174 return 0;
175}
176
177static const struct udevice_id rcar_gpio_ids[] = {
178 { .compatible = "renesas,gpio-r8a7795" },
179 { .compatible = "renesas,gpio-r8a7796" },
Marek Vasut76ed8f02018-02-26 10:35:15 +0100180 { .compatible = "renesas,gpio-r8a77965" },
Marek Vasut0f2f0d82017-10-21 11:27:04 +0200181 { .compatible = "renesas,gpio-r8a77970" },
Marek Vasut60ae40c2018-04-26 13:18:45 +0200182 { .compatible = "renesas,gpio-r8a77990" },
Marek Vasutf122c132017-10-21 11:28:06 +0200183 { .compatible = "renesas,gpio-r8a77995" },
Marek Vasute9c9e9c2021-04-27 21:29:50 +0200184 { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
Marek Vasut8b054362018-01-18 00:52:15 +0100185 { .compatible = "renesas,rcar-gen2-gpio" },
Marek Vasute3ab4242017-10-21 11:30:41 +0200186 { .compatible = "renesas,rcar-gen3-gpio" },
Hai Phama5c76132023-02-28 22:23:07 +0100187 { .compatible = "renesas,rcar-gen4-gpio", .data = RCAR_GPIO_HAS_INEN },
Marek Vasutf5f69592017-09-15 21:13:56 +0200188 { /* sentinel */ }
189};
190
191U_BOOT_DRIVER(rcar_gpio) = {
192 .name = "rcar-gpio",
193 .id = UCLASS_GPIO,
194 .of_match = rcar_gpio_ids,
195 .ops = &rcar_gpio_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700196 .priv_auto = sizeof(struct rcar_gpio_priv),
Marek Vasutf5f69592017-09-15 21:13:56 +0200197 .probe = rcar_gpio_probe,
198};